Datasheet > SY100EP210UTI

SY100EP210UTI

更新时间： 2024-09-29 23:35:43

品牌	Logo	应用领域
其他 - ETC		时钟驱动器输出元件
页数	文件大小	规格书
8页	93K
描述
TEN DISTRIBUTED-OUTPUT CLOCK DRIVER\|ECL100\|TQFP\|32PIN\|PLASTIC

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中文翻译

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数据手册

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SY100EP210UTI 数据手册

2.5V/3.3V DUAL 1:5 DIFFERENTIAL

LVECL/LVPECL/HSTL

CLOCK DRIVER

ClockWorks™

SY100EP210U

FEATURES

DESCRIPTION

■ 2.5V and 3.3V power supply options

The SY100EP210U is a high-speed, precision low skew

1-to-5 dual differential clock driver. HSTL inputs can be

used when the EP210U is operating in PECL mode.

The EP210U specifically guarantees critical AC

parameters over temperature and voltage. Optimal design,

layout, and processing minimize skew within device and

from device-to-device.

The SY100EP210U, as with most other ECL devices,

can be operated from a positive V_CCsupply in PECL mode.

This allows the EP210U to be used for high performance

clock distribution in +3.3V or +2.5V systems. Single-ended

input operation is limited to a V_CC≥ 3.0V in PECL mode, or

V_EE≤ –3.0V in ECL mode.

■ Guaranteed AC parameters over temperature:

•

f_MAX> 3.0GHz

< 35ps within-device skew

< 350ps t_r/ t_f

< 490ps propagation delay (differential)

■ Wide temperature range: –40°C to +85°C

■ Differential design

■ V_BBoutput

■ Fully compatible with industry standard 100K I/O

levels

■ Available in 32-pin TQFP Package

Designers can take advantage of the EP210U’s

performance to distribute low skew clocks across the

backplane or to multiple points on a board.

BLOCK DIAGRAM

Qa0

Qb0

/Qa0

/Qb0

Qa1

Qb1

CLKa

CLKb

V_EE

75kΩ

/Qa1

/Qb1

/CLKb

/CLKa

75kΩ

V_EEV_CC

75kΩ

Qa2

Qb2

75kΩ

V_CCV_EE

/Qa2

/Qb2

Qa3

Qb3

/Qa3

/Qb3

Qa4

Qb4

/Qa4

/Qb4

Rev.: A

Amendment: /2

Issue Date: August 2001

12 3 4 5 6 7 8

中文翻译

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