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SY100EP32VZITR PDF预览

SY100EP32VZITR

更新时间: 2024-09-30 08:56:59
品牌 Logo 应用领域
麦瑞 - MICREL /
页数 文件大小 规格书
9页 129K
描述
5V/3.3V ÷ 2 DIVIDER

SY100EP32VZITR 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP8,.25
针数:8Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.32
其他特性:OPERATES AT VCC = 5V NOM WITH VEE = 0V IN PECL MODE系列:100E
JESD-30 代码:R-PDSO-G8JESD-609代码:e0
长度:4.9 mm逻辑集成电路类型:MONOSTABLE MULTIVIBRATOR
最大频率@ Nom-Sup:4000000000 Hz湿度敏感等级:1
数据/时钟输入次数:1功能数量:1
端子数量:8最高工作温度:85 °C
最低工作温度:-40 °C输出极性:COMPLEMENTARY
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP8,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):240
电源:-3.3/-5,3.3/5 V最大电源电流(ICC):42 mA
传播延迟(tpd):0.43 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Prescaler/Multivibrators
最大供电电压 (Vsup):3.63 V最小供电电压 (Vsup):2.97 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:ECL温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3.9 mm
最小 fmax:4000 MHzBase Number Matches:1

SY100EP32VZITR 数据手册

 浏览型号SY100EP32VZITR的Datasheet PDF文件第2页浏览型号SY100EP32VZITR的Datasheet PDF文件第3页浏览型号SY100EP32VZITR的Datasheet PDF文件第4页浏览型号SY100EP32VZITR的Datasheet PDF文件第5页浏览型号SY100EP32VZITR的Datasheet PDF文件第6页浏览型号SY100EP32VZITR的Datasheet PDF文件第7页 
®  
SY10EP32V
SY100EP32V  
®
Precision Edge  
5V/3.3V ÷ 2 DIVIDER  
FEATURES  
Guaranteed maximum frequency > 4GHz  
3.3V and 5V power supply options  
ECL Pro™  
Guaranteed propagation delay <440ps over  
temperature  
DESCRIPTION  
Internal 75Kinput pull-down resistors  
Wide operating temperature range: –40°C to +85°C  
Available in 8-pin MSOP and SOIC packages  
The SY10/100EP32V is an integrated ÷2 divider with  
differential clock inputs.  
The V  
pin, an internally generated voltage supply,  
BB  
is available to this device only. For single-ended input  
conditions, the unused differential input is connected to  
V
as a switching reference voltage. V may also rebias  
BB  
BB  
PIN NAMES  
AC-coupled inputs. When used, decouple V  
and V  
CC  
BB  
via a 0.01µF capacitor and limit current sourcing or sinking  
to 0.5mA. When not used, V should be left open.  
Pin  
CLK, /CLK  
Reset  
VBB  
Function  
ECL Clock Inputs  
BB  
The reset pin is asynchronous and is asserted on the  
rising edge. Upon power-up, the internal flip-flops will  
attain a random state; the reset allows for the  
synchronous use of multiple EP32’s in a system.  
The 100k series includes internal temperature  
compensation circuitry.  
ECL Asynchronous Reset  
Reference Voltage Output  
ECL Data Outputs  
Q, /Q  
(1)  
TRUTH TABLE  
CLK  
X
/CLK  
X
RESET  
Q
L
/Q  
H
Z
L
Z
/Z  
F
F
Note 1: Z = LOW-to-HIGH Transition  
/Z = HIGH-to-LOW Transition  
F = Divide by 2 function.  
ECL Pro is a trademarks of Micrel, Inc.  
Precision Edge is a registered trademarks of Micrel, Inc.  
Rev.: D  
Amendment: /0  
M9999-111605  
hbwhelp@micrel.com or (408) 955-1690  
1
Issue Date: September2005  

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