Datasheet > SY100EP23VKITR

SY100EP23VKITR

更新时间： 2024-09-29 23:35:43

品牌	Logo	应用领域
其他 - ETC		模拟IC
页数	文件大小	规格书
8页	110K
描述
Analog IC

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中文翻译

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数据手册

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SY100EP23VKITR 数据手册

ClockWorks™

SY10EP32V

SY100EP32V

5V/3.3V ÷ 2 DIVIDER

FEATURES

DESCRIPTION

ꢀ Guaranteed maximum frequency > 4GHz

ꢀ 3.3V and 5V power supply options

The SY10/100EP32V is an integrated ÷2 divider with

differential clock inputs.

The V

pin, an internally generated voltage supply,

ꢀ Guaranteed propagation delay <440ps over

is available to this device only. For single-ended input

conditions, the unused differential input is connected to

temperature

ꢀ Internal 75KΩ input pull-down resistors

as a switching reference voltage. V may also rebias

ꢀ Wide operating temperature range: –40°C to +85°C

ꢀ Available in 8-pin MSOP and SOIC packages

AC-coupled inputs. When used, decouple V

via a 0.01µF capacitor and limit current sourcing or sinking

and V

BB CC

to 0.5mA. When not used, V should be left open.

The reset pin is asynchronous and is asserted on the

rising edge. Upon power-up, the internal flip-flops will

attain a random state; the reset allows for the

synchronous use of multiple EP32's in a system.

The 100k series includes internal temperature

compensation circuitry.

PIN NAMES

PIN CONFIGURATION/BLOCK DIAGRAM

CLK, /CLK

Reset

V_BB

Function

ECL Clock Inputs

Reset

VCC

ECL Asynchronous Reset

Reference Voltage Output

ECL Data Outputs

CLK

/CLK

VBB

÷ 2

Q, /Q

VEE

TRUTH TABLE

TOP VIEW

(Available in MSOP or SOIC package)

CLK

/CLK

RESET

NOTES:

Z = LOW-to-HIGH Transition

/Z = HIGH-to-LOW Transition

F = Divide by 2 function.

Rev.: A

Amendment:/0

Issue Date: June 2001

12 3 4 5 6 7 8

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