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SUD10P06-280L-E3 PDF预览

SUD10P06-280L-E3

更新时间: 2024-11-23 21:12:19
品牌 Logo 应用领域
威世 - VISHAY 脉冲晶体管
页数 文件大小 规格书
3页 185K
描述
Power Field-Effect Transistor, 10A I(D), 60V, 0.17ohm, 1-Element, P-Channel, Silicon, Metal-oxide Semiconductor FET, TO-252AA, DPAK-3/2

SUD10P06-280L-E3 技术参数

是否Rohs认证: 符合生命周期:Obsolete
包装说明:DPAK-3/2Reach Compliance Code:unknown
ECCN代码:EAR99风险等级:5.81
雪崩能效等级(Eas):5 mJ外壳连接:DRAIN
配置:SINGLE WITH BUILT-IN DIODE最小漏源击穿电压:60 V
最大漏极电流 (Abs) (ID):10 A最大漏极电流 (ID):10 A
最大漏源导通电阻:0.17 ΩFET 技术:METAL-OXIDE SEMICONDUCTOR
JEDEC-95代码:TO-252AAJESD-30 代码:R-PSSO-G2
JESD-609代码:e3湿度敏感等级:1
元件数量:1端子数量:2
工作模式:ENHANCEMENT MODE最高工作温度:175 °C
封装主体材料:PLASTIC/EPOXY封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):260
极性/信道类型:P-CHANNEL最大功率耗散 (Abs):2 W
最大脉冲漏极电流 (IDM):20 A子类别:Other Transistors
表面贴装:YES端子面层:Matte Tin (Sn) - with Nickel (Ni) barrier
端子形式:GULL WING端子位置:SINGLE
处于峰值回流温度下的最长时间:30晶体管元件材料:SILICON
Base Number Matches:1

SUD10P06-280L-E3 数据手册

 浏览型号SUD10P06-280L-E3的Datasheet PDF文件第2页浏览型号SUD10P06-280L-E3的Datasheet PDF文件第3页 
SPICE Device Model SUD10P06-280L  
Vishay Siliconix  
P-Channel 60-V (D-S) MOSFET  
CHARACTERISTICS  
P-Channel Vertical DMOS  
Macro Model (Subcircuit Model)  
Level 3 MOS  
Apply for both Linear and Switching Application  
Accurate over the 55 to 125°C Temperature Range  
Model the Gate Charge, Transient, and Diode Reverse Recovery  
Characteristics  
DESCRIPTION  
The attached spice model describes the typical electrical  
characteristics of the p-channel vertical DMOS. The subcircuit  
model is extracted and optimized over the 55 to 125°C  
temperature ranges under the pulsed 0-V to 5-V gate drive. The  
saturated output impedance is best fit at the gate bias near the  
threshold voltage.  
A novel gate-to-drain feedback capacitance network is used to model  
the gate charge characteristics while avoiding convergence difficulties  
of the switched Cgd model. All model parameter values are optimized  
to provide a best fit to the measured electrical data and are not  
intended as an exact physical interpretation of the device.  
SUBCIRCUIT MODEL SCHEMATIC  
This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate  
data sheet of the same number for guaranteed specification limits.  
www.vishay.com  
Document Number: 71721  
S-52575Rev. B, 02-Jan-06  
1

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