Datasheet > STW51000AT

STW51000AT

更新时间： 2024-11-17 04:01:39

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
8页	221K
描述
SUPER INTEGRATED DSP ENGINE

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STW51000AT 数据手册

GreenSIDE

STW51000

SUPER INTEGRATED DSP ENGINE

DATA BRIEF

1 Product Features

Figure 1. Package

■ Super Integrated SoC including 2 x ST140 quad

MAC DSP engines running at 600MHz and 1 x

ARM926 Micro Controller running at 300MHz

■ Double Quad-MAC units

■ Double Quad-ALU (32 and 40-bit)

■ 4800 MMacs/s - 29000 Mops - 7500 Mips

■ Convolutional Decoder Engine:

– 256 x 12.2 kpbs AMR voice users

– Programmable Code Parameters to support

multi-standards (W-CDMA, TD-SCDMA,

CDMA2000 and EDGE)

PBGA/HSP-569

Table 1. Order Codes

Part Number

Package

STW51000AT

PBGA/HSP-569

■ Turbo Decoder Engine:

■ Conditional Instructions to reduce code size and

overhead

– 28 x 384 kbps (8 iterations)

■ Built-in Coprocessor Interfaces for highly

optimized Instruction Definition

■ Compiler Friendly Instruction Set for high

performance critical DSP Routines directly from

■ 8, 16, 32 and 40-bit Data Support

■ Circular and bit-reversed Data addressing

modes

■ 32x16 bit Multiplier eases floating point to fixed

point conversion

■ 8-bit Overflow protection

■ Bit Manipulation

■ Normalization, Saturation

■ Zero Overhead Loops

– Programmable Code Parameters to support

multi-standards (W-CDMA, TD-SCDMA and

CDMA2000)

– Includes CRC Processing

– Hardware Interleaver with multi-standard

support

■ Two 32-channel DMA Engines

■ 16Mbit Central Memory shared among DSPs,

µC and DMA Engines

■ One 32-bit External Memory Controller

■ One external Master Interface

■ One 32-bit Communication Interface

■ Two Multi-Channel Serial Ports

■ Two Ethernet MAC

■ 32Kbytes L1 Program Cache and 64Kbytes L1

Data Cache

■ One 16-bit UTOPIA Level 2 Interface

■ 32-bit General Purpose I/Os

■ Two 32-bit Timers

■ Programmable PLL Clock Generator

■ IEEE-1149.1 (JTAG)

■ Development tools available

■ Baseband modem SW deliverables available

3 ARM926 Features

■ 32/16-bit RISC Architecture

■ 32-bit ARM Instruction Set for maximum

performance and flexibility

■ 16-bit Thumb Instruction set for high code

density

■ Built-in Memory Management Unit for OS

Support

■ 32Kbytes L1 Program Cache

■ 16KBytes L1 Data Cache

2 ST140 Features

■ 32-bit Load/Store Architecture

■

16-bit, 32-bit or 128-bit (SLIW) Instruction Set for

high performance / high code density trade off

Rev. 2

1/8

April 2005

This is preliminary information on a new product now in development. Details are subject to change without notice.

12 3 4 5 6 7 8

中文翻译

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