Datasheet > STLS2E02

STLS2E02

更新时间： 2024-09-28 03:30:51

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		微处理器
页数	文件大小	规格书
5页	114K
描述
Loongson 2E: 700MHz 64-bit superscalar MIPS㈢ based microprocessor

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STLS2E02 数据手册

STLS2E02

Loongson 2E:

700MHz 64-bit superscalar MIPS® based microprocessor

Data Brief

Features

■ 64 bit superscalar architecture

■ 700MHz clock frequency (typical conditions)

■ Single/double precision floating-point units

■ New Streaming Multimedia instruction set

support (SIMD)

■ 64KB instruction cache, 64KB data cache, on-

chip 512KB unified L2 cache

■ On-chip DDR-333 controller

PBGA452

■ Thermal Design Power (TDP)

– 4W @ 700MHz

■ Leading edge 90nm process technology

■ 35x35 BGA package

The memory hierarchy is composed by the first

level of 64KB 4-way set associative cache for

instructions and data, the second level of 512KB

unified 4-ways set associative cache and the

Memory Management Unit with Table Lookside

Buffer.

■ MIPS based

■ MIPS bus interface (Sysad)

Description

The STLS2E02, is a MIPS based 64-bit

superscalar microprocessor, able to issue four

instructions per clock cycle among six functional

units: two integer, two single/double-precision

floating-point, one 64bit SIMD and one load/store

unit.

The Loongson microprocessor family is the

outcome of a successful collaboration started in

2004 between STMicroelectronics and the

Institute of Computing Technology, part of the

Chinese Academy of Science. Loongson

microprocessors were co-developed by

STMicroelectronics and the Institute of

Computing Technology to address all the

applications requiring high level of performance

and low power dissipation.

The microarchitecture is organized with nine

stages of pipeline and support of dynamic branch

prediction.

Table 1.

Device summary

Part numbers

Package

PBGA452 (35x35x2.33mm)

Packing

STLS2E02

Tray

April 2007

Rev 2

1/5

For further information contact your local STMicroelectronics sales office.

www.st.com

12 3 4 5

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