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STLS2F01 PDF预览

STLS2F01

更新时间: 2024-09-28 03:30:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 微处理器
页数 文件大小 规格书
48页 680K
描述
Loongson 2F: High performance 64-bit superscalar MIPS㈢ microprocessor

STLS2F01 数据手册

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STLS2F01  
Loongson 2F:  
High performance 64-bit superscalar MIPS® microprocessor  
Preliminary Data  
Features  
64-bit superscalar architecture  
900 MHz clock frequency  
Single/double precision floating-point units  
New streaming multimedia instruction set  
support (SIMD)  
64 Kbyte instruction cache, 64 Kbyte data  
HFCBGA452 (27x27x2.9mm)  
cache, on-chip 512 Kbyte unified L2 cache  
On chip DDR2-667 and PCI-X controller  
The memory hierarchy is composed by the first  
level of 64 Kbyte 4-way set associative caches for  
instructions and data, the second level of  
512 Kbyte unified 4-way set associative cache  
and the memory management unit (MMU) with  
translation lookaside buffer (TLB).  
4 W @ 900 MHz power consumption:  
– Best in class for power management  
– Voltage/frequency scaling  
– Stand-by mode support  
– L2 cache disable/enable option  
The Loongson microprocessor family is the  
outcome of a successful collaboration started in  
2004 between STMicroelectronics and the  
Institute of Computing Technology, part of the  
Chinese Academy of Science. Loongson  
microprocessors were co-developed by  
STMicroelectronics and the Institute of  
Computing Technology to address all the  
applications requiring high level of performance  
and low power dissipation.  
Leading edge 90 nm process technology  
27x27 heat spreader flip-chip BGA package  
MIPS based instruction set (MIPS III  
compatible)  
Description  
The STLS2F01 is a MIPS based 64-bit  
superscalar microprocessor, able to issue four  
instructions per clock cycle among six functional  
units: two integer, two single/double-precision  
floating-point, one 64bit SIMD and one load/store  
unit.  
Compared to the STLS2E02 processor, the  
STLS2F01 has an enhanced architecture  
providing higher performance, reduced power  
consumption, integrated DDR2 memory controller  
and PCI-X bus interface.  
The micro architecture is organized with nine-  
stage of pipeline and support of dynamic branch  
prediction.  
Table 1.  
Device summary  
Part numbers  
Package  
HFCBGA452 (27x27x2.9mm)  
Packing  
STLS2F01  
Tray  
May 2008  
Rev 1  
1/48  
This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to  
change without notice.  
www.st.com  
1

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