Datasheet > 存储 > SRAM> STK15C88-NF45TR

STK15C88-NF45TR

更新时间： 2024-01-23 16:53:50

品牌	Logo	应用领域
SIMTEK		静态存储器
页数	文件大小	规格书
15页	403K
描述
32Kx8 PowerStore nvSRAM

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数据手册

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STK15C88-NF45TR 数据手册

STK15C88

SRAM READ CYCLES #1 & #2 (V_CC= 5.0V ± 10%)

SYMBOLS

STK15C88-25 STK15C88-45

PARAMETER

UNITS

NO.

#1, #2

Alt.

MIN

MAX

MIN

MAX

Chip Enable Access Time

ELQV

ACS

_AVAV^f, t

Read Cycle Time

ELEH

Address Access Time

AVQV

Output Enable to Data Valid

GLQV

Output Hold after Address Change

Address Change or Chip Enable to Output Active

Address Change or Chip Disable to Output Inactive

Output Enable to Output Active

Output Disable to Output Inactive

Chip Enable to Power Active

AXQX

ELQX

EHQZ

GLQX

OLZ

OHZ

GHQZ

ELICCH

Chip Disable to Power Standby

EHICCL

Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.

Note g: I/O state assumes E, G < V_ILand W > V_IH; device is continuously selected.

Note h: Measured + 200mV from steady state output voltage.

SRAM READ CYCLE #1: Address Controlled^{f, g}

AVAV

ADDRESS

AVQV

AXQX

DATA VALID

DQ (DATA OUT)

SRAM READ CYCLE #2: E and G Controlled^f

ADDRESS

t_{E LE H}

t_EHAX

t_{EHI CC L}

t_{EL Q V}

t_{ELQ X}

t_{EHQ Z}

t_{AV QV}

t_{G L QV}

t_{GH Q Z}

t_{G L Q X}

DQ (D ATA OUT)

DATA VAL ID

t_{ELI CC H}

AC TIVE

STAND BY

I_CC

Rev 2.0

Document Control #ML0016

Jan, 2008

1 2 345 6 7...15

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