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STK14C88-K35I PDF预览

STK14C88-K35I

更新时间: 2024-10-27 22:53:23
品牌 Logo 应用领域
其他 - ETC 存储内存集成电路静态存储器
页数 文件大小 规格书
13页 370K
描述
32K x 8 AutoStore nvSRAM QuantumTrap CMOS Nonvolatile Static RAM

STK14C88-K35I 数据手册

 浏览型号STK14C88-K35I的Datasheet PDF文件第1页浏览型号STK14C88-K35I的Datasheet PDF文件第2页浏览型号STK14C88-K35I的Datasheet PDF文件第4页浏览型号STK14C88-K35I的Datasheet PDF文件第5页浏览型号STK14C88-K35I的Datasheet PDF文件第6页浏览型号STK14C88-K35I的Datasheet PDF文件第7页 
STK14C88  
SRAM READ CYCLES #1 & #2  
(VCC = 5.0V ± 10%)e  
SYMBOLS  
STK14C88-25  
STK14C88-35  
STK14C88-45  
NO.  
PARAMETER  
UNITS  
#1, #2  
Alt.  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
25  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
RC  
AA  
g
Read Cycle Time  
25  
35  
45  
AVAV  
h
3
Address Access Time  
25  
10  
35  
15  
45  
20  
AVQV  
4
Output Enable to Data Valid  
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
GLQV  
OE  
OH  
LZ  
h
5
5
5
5
5
5
5
AXQX  
6
ELQX  
i
7
10  
10  
25  
13  
13  
35  
15  
15  
45  
EHQZ  
HZ  
8
0
0
0
0
0
0
GLQX  
OLZ  
OHZ  
PA  
i
9
GHQZ  
f
f
10  
11  
ELICCH  
EHICCL  
PS  
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.  
Note h: I/O state assumes E and G < V and W > V ; device is continuously selected.  
IL  
IH  
Note i: Measured ± 200mV from steady state output voltage.  
SRAM READ CYCLE #1: Address Controlledg, h  
2
t
AVAV  
ADDRESS  
3
t
AVQV  
5
t
AXQX  
DQ (DATA OUT)  
DATA VALID  
SRAM READ CYCLE #2: E Controlledg  
2
t
AVAV  
ADDRESS  
E
1
11  
t
ELQV  
t
EHICCL  
6
t
ELQX  
7
t
EHQZ  
G
9
4
t
GHQZ  
t
GLQV  
8
t
GLQX  
DATA VALID  
DQ (DATA OUT)  
10  
t
ELICCH  
ACTIVE  
STANDBY  
I
CC  
December 2002  
3
Document Control # ML0014 rev 0.0  
 
 
 

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