Datasheet > STK12C68-5

STK12C68-5

更新时间： 2022-12-23 03:42:49

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		存储静态存储器
页数	文件大小	规格书
18页	575K
描述
64 Kbit (8K x 8) AutoStore nvSRAM

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数据手册

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STK12C68-5 数据手册

STK12C68-5 (SMD5962-94599)

Pinouts

Figure 1. Pin Diagram - 28-Pin DIP

Figure 2. Pin Diagram - 28-Pin LLC

Pin Definitions

Pin Name Alt

IO Type

Description

Address Inputs. Used to select one of the 8,192 bytes of the nvSRAM.

A₀–A₁₂

Input

DQ₀-DQ₇

Input or Output Bidirectional Data IO Lines. Used as input or output lines depending on operation.

Input

Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the IO

pins is written to the specific address location.

Input

Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the

chip.

Input

Output Enable, Active LOW. The active LOW OEinput enables the data output buffers during

read cycles. Deasserting OE HIGH causes the IO pins to tri-state.

V_SS

V_CC

Ground

Ground for the Device. The device is connected to ground of the system.

Power Supply Power Supply Inputs to the Device.

Input or Output Hardware Store Busy (HSB). When LOW, this output indicates a Hardware Store is in

progress. When pulled low external to the chip, it initiates a nonvolatile STORE operation. A

weak internal pull up resistor keeps this pin high if not connected (connection optional).

HSB

V_CAP

Power Supply AutoStoreCapacitor. Supplies power to nvSRAM during power loss to store data from SRAM

to nonvolatile elements.

Document Number: 001-51026 Rev. **

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与STK12C68-5相关器件

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STK12C68-5C25	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25I	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C25M	ETC	8K x 8 AutoStore⑩ nvSRAM QuantumTrap⑩ CMOS No	获取价格
STK12C68-5C30	CYPRESS	8KX8 NON-VOLATILE SRAM, 30ns, CDIP28, 0.300 INCH, CERAMIC, DIP-28	获取价格
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