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ST7LITE20F2 PDF预览

ST7LITE20F2

更新时间: 2024-11-11 12:02:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存存储微控制器可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
166页 1378K
描述
8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, Timers, SPI

ST7LITE20F2 数据手册

 浏览型号ST7LITE20F2的Datasheet PDF文件第2页浏览型号ST7LITE20F2的Datasheet PDF文件第3页浏览型号ST7LITE20F2的Datasheet PDF文件第4页浏览型号ST7LITE20F2的Datasheet PDF文件第5页浏览型号ST7LITE20F2的Datasheet PDF文件第6页浏览型号ST7LITE20F2的Datasheet PDF文件第7页 
ST7LITE20F2 ST7LITE25F2 ST7LITE29F2  
8-bit microcontroller with single voltage Flash memory,  
data EEPROM, ADC, Timers, SPI  
Datasheet production data  
4 timers  
– Configurable watchdog timer  
Two 8-bit Lite timers with prescaler  
– 1 real-time base and 1 input capture  
– One 12-bit auto-reload timer with 4 PWM  
DIP20  
outputs, input capture and output compare  
functions.  
SO20 300”  
1 communication interface  
– SPI synchronous serial interface.  
Features  
Interrupt management  
– 10 interrupt vectors plus TRAP and RESET  
– 15 external interrupt lines (on 4 vectors).  
Memories  
– 8 Kbytes single voltage Flash Program  
memory with Read-out protection  
A/D converter  
– 7 input channels  
– In-circuit programming and in-application  
programming (ICP and IAP)  
– Fixed gain op-amp  
– 10K write/erase cycles guaranteed  
– Data retention: 20 years at 55 °C  
Temperature range: -40°C to 105°C  
– 384 bytes RAM.  
– 13-bit resolution for 0 to 430 mV (@ 5 V  
VDD  
)
– 10-bit resolution for 430 mV to 5 V (@ 5 V  
VDD).  
Instruction set  
Clock, reset and supply management  
– 8-bit data manipulation  
– Enhanced reset system  
– 63 basic instructions with illegal opcode  
detection  
– 17 main addressing modes  
– Enhanced low voltage supervisor (LVD) for  
main supply and an auxiliary voltage  
detector (AVD) with interrupt capability for  
implementing safe power-down procedures  
– 8 x 8 unsigned multiply instructions.  
– Clock sources: internal 1% RC oscillator,  
crystal/ceramic resonator or external clock  
– Internal 32-MHz input clock for auto-reload  
timer  
Development tools  
– Full hardware/software development  
package  
– DM (debug module)  
– Optional x4 or x8 PLL for 4 or 8 MHz  
internal clock  
– Five power saving modes: Halt, Active-halt,  
Wait and Slow, Auto-wakeup from Halt.  
I/O ports  
– Up to 15 multifunctional bidirectional I/O  
lines  
– 7 high sink outputs.  
June 2013  
Doc ID 8349 Rev 5  
1/166  
This is information on a product in full production.  
www.st.com  
1
 

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