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ST72F521AR9T3/XXX PDF预览

ST72F521AR9T3/XXX

更新时间: 2024-11-03 20:02:43
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 时钟微控制器外围集成电路
页数 文件大小 规格书
195页 1191K
描述
IC,MICROCONTROLLER,8-BIT,ST72 CPU,CMOS,QFP,64PIN,PLASTIC

ST72F521AR9T3/XXX 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Contact Manufacturer零件包装代码:QFP
包装说明:LFQFP, QFP64,.47SQ,20针数:64
Reach Compliance Code:compliant风险等级:5.8
具有ADC:YES地址总线宽度:
位大小:8CPU系列:ST72
最大时钟频率:16 MHzDMA 通道:NO
外部数据总线宽度:JESD-30 代码:S-PQFP-G64
JESD-609代码:e4长度:10 mm
I/O 线路数量:48端子数量:64
最高工作温度:125 °C最低工作温度:-40 °C
PWM 通道:YES封装主体材料:PLASTIC/EPOXY
封装代码:LFQFP封装等效代码:QFP64,.47SQ,20
封装形状:SQUARE封装形式:FLATPACK, LOW PROFILE, FINE PITCH
峰值回流温度(摄氏度):NOT SPECIFIED电源:3.3/5 V
认证状态:Not QualifiedRAM(字节):2048
ROM(单词):61440ROM可编程性:FLASH
速度:8 MHz子类别:Microcontrollers
最大压摆率:8 mA最大供电电压:5.5 V
最小供电电压:3.8 V标称供电电压:5 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.5 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:10 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER, RISC
Base Number Matches:1

ST72F521AR9T3/XXX 数据手册

 浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第2页浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第3页浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第4页浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第5页浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第6页浏览型号ST72F521AR9T3/XXX的Datasheet PDF文件第7页 
ST72521M/R/AR  
8-BIT MCU WITH NESTED INTERRUPTS, FLASH, 10-BIT ADC,  
2
FIVE TIMERS, SPI, SCI, I C, CAN INTERFACE  
PRODUCT PREVIEW  
Memories  
– 32K to 60K dual voltage High Density Flash  
(HDFlash) or ROM with read-out protection  
capability. In-Application Programming and  
In-Circuit Programming for HDFlash devices  
– 1K to 2K RAM  
Clock, Reset And Supply Management  
TQFP64  
14 x 14  
– Enhanced reset system  
TQFP64  
10 x 10  
– Enhanced low voltage supervisor (LVD) for  
main supply with 3 programmable reset  
thresholds and auxiliary voltage detector  
(AVD) with interrupt capability  
TQFP80  
14 x 14  
– Clock sources: crystal/ceramic resonator os-  
cillators or RC oscillator with PLL and by-pass  
for external clock, clock security system.  
4 Communications Interfaces  
– SPI synchronous serial interface  
– SCI asynchronous serial interface  
– Four power saving modes: Halt, Active-Halt,  
Wait and Slow  
2
Interrupt Management  
– I C multimaster interface  
– CAN interface (2.0B Passive)  
– Nested interrupt controller  
Analog peripheral  
– 14 interrupt vectors plus TRAP and RESET  
– TLI dedicated top level interrupt pin  
– 15 external interrupt lines (on 4 vectors)  
Up to 64 I/O Ports  
– 10-bit ADC with 16 input pins  
Instruction Set  
– 48 multifunctional bidirectional I/O lines  
– 34 alternate function lines  
– 16 high sink outputs  
– 8-bit Data Manipulation  
– 63 Basic Instructions  
– 17 main Addressing Modes  
– 8 x 8 Unsigned Multiply Instruction  
– True Bit Manipulation  
5 Timers  
– Main Clock Controller with: Real time base,  
Beep and Clock-out capabilities  
– Configurable watchdog timer  
Development Tools  
– Two 16-bittimers with: 2 input captures, 2 out-  
put compares, external clock input on one tim-  
er, PWM and pulse generator modes  
– 8-bit PWM Auto-Reload timer with: 2 input  
captures, 4 PWM outputs, output compare  
and time base interrupt, external clock with  
event detector  
– Full hardware/software development package  
– In-Circuit Testing capability  
Device Summary  
Features  
Program memory - bytes  
RAM (stack) - bytes  
ST72(F)521(M/R/AR)9  
60K  
ST72(F)521(M/R/AR)7  
ST72521(R/AR)6  
32K  
48K  
2048 (256)  
1536 (256)  
1024 (256)  
Watchdog, 16-bit Timers, 8-bit PWM ART, SPI, SCI, 10-bit ADC, CAN  
Peripherals  
2
I C  
-
Operating  
Supply vs. Frequency  
FLASH: 2.7 to 5.5V with f  
4MHz or 3.85V to 5.5V with f  
8MHz  
CPU  
CPU  
ROM: 2.7 to 5.5V with f  
8MHz  
CPU  
ROM: 2.7 to 5.5V with f  
8MHz  
CPU  
Temperature Range  
Package  
0°C to 70°C / -10°C to +85 °C / -40°C to +85 °C / -40°C to +105°C / -40°C to +125°C  
TQFP80 14x14 (M), TQFP64 14x14 (R), TQFP64 10x10 (AR)  
TQFP64 14x14 (R), TQFP64 10x10 (AR)  
Rev. 1.3  
1/195  
February 2001  
This ispreliminary information on a new product in development or undergoing evaluation. Details aresubject to change without notice.  
1

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