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SST89E554A-40-I-NJ PDF预览

SST89E554A-40-I-NJ

更新时间： 2024-11-12 15:52:59
品牌 Logo 应用领域
芯科 - SILICON 时钟PC微控制器外围集成电路
页数 文件大小 规格书
87页 909K
描述
Microcontroller, 8-Bit, FLASH, 40MHz, CMOS, PQCC44, PLASTIC, MS-018AC, LCC-44

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SST89E554A-40-I-NJ 技术参数

生命周期：Obsolete零件包装代码：LPCC
包装说明：QCCJ,针数：44
Reach Compliance Code：unknownECCN代码：3A991.A.2
HTS代码：8542.31.00.01风险等级：5.84
Is Samacsys：N具有ADC：NO
地址总线宽度：16位大小：8
最大时钟频率：40 MHzDAC 通道：NO
DMA 通道：NO外部数据总线宽度：8
JESD-30 代码：S-PQCC-J44长度：16.5354 mm
I/O 线路数量：36端子数量：44
最高工作温度：85 °C最低工作温度：-40 °C
PWM 通道：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装形状：SQUARE
封装形式：CHIP CARRIER认证状态：Not Qualified
ROM可编程性：FLASH座面最大高度：4.57 mm
速度：40 MHz最大供电电压：5.5 V
最小供电电压：4.5 V标称供电电压：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
宽度：16.5354 mmuPs/uCs/外围集成电路类型：MICROCONTROLLER
Base Number Matches：1

SST89E554A-40-I-NJ 数据手册

 浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第2页浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第3页浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第4页浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第5页浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第6页浏览型号SST89E554A-40-I-NJ的Datasheet PDF文件第7页 
FlashFlex51 MCU  
SST89E554A / SST89V554A  
SST89E/VE554A FlashFlex51 MCU  
Preliminary Specifications  
FEATURES:  
•
8-bit 8051-Compatible Microcontroller (MCU)  
with Embedded SuperFlash Memory  
•
Ten Interrupt Sources at 4 Priority Levels  
– Four External Interrupt Inputs  
– Fully Software Compatible  
– Development Toolset Compatible  
– Pin-For-Pin Package Compatible  
•
•
•
Programmable Watchdog Timer (WDT)  
Programmable Counter Array (PCA)  
Four 8-bit I/O Ports (32 I/O Pins) and  
One 4-bit Port  
Second DPTR register  
Low EMI Mode (Inhibit ALE)  
SPI Serial Interface  
Standard 12 Clocks per cycle, the device has an  
option to double the speed to 6 clocks per cycle.  
•
•
SST89E554A Operation  
– 0 to 40 MHz at 5V  
SST89V554A Operation  
– 0 to 33 MHz at 3V  
•
•
•
•
•
•
1 KByte Internal RAM  
Dual Block SuperFlash EEPROM  
– 32 KByte primary block + 8 KByte secondary  
block (128-Byte sector size for both blocks)  
– Individual Block Security Lock with SoftLock  
– Concurrent Operation during  
•
•
•
TTL- and CMOS-Compatible Logic Levels  
Brown-out Detection  
Low Power Modes  
In-Application Programming (IAP)  
– Memory Overlay for Interrupt Support during IAP  
– Power-down Mode with External Interrupt Wake-up  
– Idle Mode  
•
Support External Address Range up to 64  
KByte of Program and Data Memory  
Three High-Current Drive Ports (16 mA each)  
Three 16-bit Timers/Counters  
•
•
Temperature Ranges:  
– Commercial (0°C to +70°C)  
– Industrial (-40°C to +85°C)  
•
•
•
Packages Available  
– 44-lead PLCC  
Full-Duplex, Enhanced UART  
– 40-pin PDIP (Port 4 feature not available)  
– 44-lead TQFP  
– Framing Error Detection  
– Automatic Address Recognition  
PRODUCT DESCRIPTION  
The SST89E554A and SST89V554A are members of the  
FlashFlex51 family of 8-bit microcontroller products  
designed and manufactured with SST’s patented and pro-  
prietary SuperFlash CMOS semiconductor process tech-  
nology. The split-gate cell design and thick-oxide tunneling  
injector offer significant cost and reliability benefits for SST’s  
customers. The devices use the 8051 instruction set and  
are pin-for-pin compatible with standard 8051 microcontrol-  
ler devices.  
In addition to the 40 KByte of EEPROM program memory  
on-chip, the devices can address up to 64 KByte of exter-  
nal program memory. In addition to 1024 x8 bits of on-chip  
RAM, up to 64 KByte of external RAM can be addressed.  
The flash memory blocks can be programmed via a stan-  
dard 87C5x OTP EPROM programmer fitted with a special  
adapter and the firmware for SST’s devices. During power-  
on reset, the devices can be configured as either a slave to  
an external host for source code storage or a master to an  
external host for an in-application programming (IAP) oper-  
ation. The devices are designed to be programmed in-sys-  
tem and in-application on the printed circuit board for  
maximum flexibility. The devices are pre-programmed with  
an example of the bootstrap loader in the memory, demon-  
strating the initial user program code loading or subsequent  
user code updating via the IAP operation. The sample  
bootstrap loader is available for the user’s reference and  
convenience only; SST does not guarantee its functionality  
or usefulness. Chip-Erase or Block-Erase operations will  
erase the pre-programmed sample code.  
The devices come with 40 KByte of on-chip flash  
EEPROM program memory which is partitioned into 2  
independent program memory blocks. The primary Block 0  
occupies 32 KByte of internal program memory space and  
the secondary Block 1 occupies 8 KByte of internal pro-  
gram memory space.  
The 8-KByte secondary block can be mapped to the lowest  
location of the 32 KByte address space; it can also be hid-  
den from the program counter and used as an independent  
EEPROM-like data memory.  
©2003 Silicon Storage Technology, Inc.  
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71228-00-000  
1
6/03  
 
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