FlashFlex51 MCU
SST89E52RD2/RD / SST89E54RD2/RD / SST89E58RD2/RD
SST89V52RD2/RD / SST89V54RD2/RD / SST89V58RD2/RD
SST89E/V58 / 54 / 52RD2/RD FlashFlex51 MCU
Data Sheet
FEATURES:
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8-bit 8051-Compatible Microcontroller (MCU)
with Embedded SuperFlash Memory
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Ten Interrupt Sources at 4 Priority Levels
– Four External Interrupt Inputs
– Fully Software Compatible
– Development Toolset Compatible
– Pin-For-Pin Package Compatible
SST89E5xRD2 Operation
– 0 to 40 MHz at 5V
SST89V5xRD2 Operation
– 0 to 33 MHz at 3V
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Programmable Watchdog Timer (WDT)
Programmable Counter Array (PCA)
Four 8-bit I/O Ports (32 I/O Pins) and
One 4-bit Port
Second DPTR register
Low EMI Mode (Inhibit ALE)
SPI Serial Interface
Standard 12 Clocks per cycle, the device has an
option to double the speed to 6 clocks per cycle.
TTL- and CMOS-Compatible Logic Levels
Brown-out Detection
Low Power Modes
– Power-down Mode with External Interrupt Wake-up
– Idle Mode
Temperature Ranges:
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1 KByte Internal RAM
Dual Block SuperFlash EEPROM
– 8/16/32 KByte primary block +
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8 KByte secondary block
(128-Byte sector size for both blocks)
– Individual Block Security Lock with SoftLock
– Concurrent Operation during
In-Application Programming (IAP)
– Memory Overlay for Interrupt Support during IAP
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Support External Address Range up to 64
KByte of Program and Data Memory
Three High-Current Drive Ports (16 mA each)
Three 16-bit Timers/Counters
– Commercial (0°C to +70°C)
– Industrial (-40°C to +85°C)
Packages Available
– 40-contact WQFN (Port 4 feature not available)
– 44-lead PLCC
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Full-Duplex, Enhanced UART
– 40-pin PDIP (Port 4 feature not available)
– 44-lead TQFP
– Framing Error Detection
– Automatic Address Recognition
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All non-Pb (lead-free) devices are RoHS compliant
PRODUCT DESCRIPTION
The SST89E5xRD2/RD and SST89V5xRD2/RD are
members of the FlashFlex51 family of 8-bit microcontroller
products designed and manufactured with SST’s patented
and proprietary SuperFlash CMOS semiconductor pro-
cess technology. The split-gate cell design and thick-oxide
tunneling injector offer significant cost and reliability bene-
fits for SST’s customers. The devices use the 8051 instruc-
tion set and are pin-for-pin compatible with standard 8051
microcontroller devices.
In addition to the 16/24/40 KByte of EEPROM program
memory on-chip, the devices can address up to 64 KByte
of external program memory. In addition to 1024 x8 bits of
on-chip RAM, up to 64 KByte of external RAM can be
addressed.
The flash memory blocks can be programmed via a stan-
dard 87C5x OTP EPROM programmer fitted with a special
adapter and the firmware for SST’s devices. During power-
on reset, the devices can be configured as either a slave to
an external host for source code storage or a master to an
external host for an in-application programming (IAP) oper-
ation. The devices are designed to be programmed in-sys-
tem and in-application on the printed circuit board for
maximum flexibility. The devices are pre-programmed with
an example of the bootstrap loader in the memory, demon-
strating the initial user program code loading or subsequent
user code updating via the IAP operation. The sample
bootstrap loader is available for the user’s reference and
convenience only; SST does not guarantee its functionality
or usefulness. Chip-Erase or Block-Erase operations will
erase the pre-programmed sample code.
The devices come with 16/24/40 KByte of on-chip flash
EEPROM program memory which is partitioned into 2
independent program memory blocks. The primary Block 0
occupies 8/16/32 KByte of internal program memory space
and the secondary Block 1 occupies 8 KByte of internal
program memory space.
The 8-KByte secondary block can be mapped to the lowest
location of the 8/16/32 KByte address space; it can also be
hidden from the program counter and used as an indepen-
dent EEPROM-like data memory.
©2006 Silicon Storage Technology, Inc.
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
S71255-05-000
1
5/06