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SST89C58-33-I-PIE PDF预览

SST89C58-33-I-PIE

更新时间: 2024-11-25 15:52:59
品牌 Logo 应用领域
芯科 - SILICON 时钟微控制器光电二极管外围集成电路
页数 文件大小 规格书
52页 967K
描述
Microcontroller, 8-Bit, FLASH, 8051 CPU, 33MHz, CMOS, PDIP40, LEAD FREE, PLASTIC, DIP-40

SST89C58-33-I-PIE 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:DIP包装说明:DIP, DIP40,.6
针数:40Reach Compliance Code:unknown
ECCN代码:3A991.A.2HTS代码:8542.31.00.01
风险等级:5.76具有ADC:NO
其他特性:ALSO OPERATES AT 2.7V MINIMUM SUPPLY地址总线宽度:16
位大小:8CPU系列:8051
最大时钟频率:33 MHzDAC 通道:NO
DMA 通道:NO外部数据总线宽度:8
JESD-30 代码:R-PDIP-T40长度:51.943 mm
I/O 线路数量:32端子数量:40
最高工作温度:85 °C最低工作温度:-40 °C
PWM 通道:NO封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP40,.6
封装形状:RECTANGULAR封装形式:IN-LINE
电源:3/5 V认证状态:Not Qualified
RAM(字节):256ROM(单词):32768
ROM可编程性:FLASH座面最大高度:5.588 mm
速度:33 MHz子类别:Microcontrollers
最大压摆率:88 mA最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:INDUSTRIAL端子形式:THROUGH-HOLE
端子节距:2.54 mm端子位置:DUAL
宽度:15.24 mmuPs/uCs/外围集成电路类型:MICROCONTROLLER
Base Number Matches:1

SST89C58-33-I-PIE 数据手册

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FlashFlex51 MCU  
SST89C54 / SST89C58  
SST89C5xFlashFlex51 MCU  
Data Sheet  
FEATURES:  
8-bit 8051-Compatible Microcontroller (MCU)  
Support External Address Range up to 64  
with Embedded SuperFlash Memory  
KByte of Program and Data Memory  
Three High Current Drive Ports (16 mA each)  
Three 16-bit Timers/Counters  
– Fully Software Compatible  
– Development Toolset Compatible  
– Pin-For-Pin Package Compatible  
SST89C54/58 Operation  
– 0 to 33MHz at 5V  
256 Bytes Internal RAM  
Dual Block SuperFlash EEPROM  
Full-Duplex Serial Port (UART)  
Six Interrupt Sources at 2 Priority Levels  
Programmable Watchdog Timer (WDT)  
Four 8-bit I/O Ports (32 I/O Pins)  
TTL- and CMOS-Compatible Logic Levels  
Low Power Modes  
– SST89C58:  
32 KByte primary block (128-Byte sector size) +  
4 KByte secondary block (64-Byte sector size)  
– SST89C54:  
– Power-down Mode with External Interrupt Wake-up  
– Standby (Stop Clock)  
16 KByte primary block (128-Byte sector size) +  
4 KByte secondary block (64-Byte sector size)  
– Individual Block Security Lock with SoftLock  
– Concurrent Operation during  
In-Application Programming (IAP)  
– Memory Overlay for Interrupt Support  
during IAP  
Low Voltage at 2.7V (0 to 12MHz)  
Temperature Ranges:  
– Commercial (0°C to +70°C)  
– Industrial (-40°C to +85°C)  
PDIP-40, PLCC-44 and TQFP-44 Packages  
PRODUCT DESCRIPTION  
The SST89C54 and SST89C58 are members of the  
FlashFlex51 family of 8-bit microcontroller products  
designed and manufactured with SST’s patented and  
proprietary SuperFlash CMOS semiconductor process  
technology. The split-gate cell design and thick-oxide tun-  
neling injector offer significant cost and reliability benefits  
for our customers. The devices use the 8051 instruction  
set and are pin-for-pin compatible with standard 8051  
microcontroller devices.  
In addition to 20/36 KByte of EEPROM program memory  
on-chip, the devices can address up to 64 KByte of exter-  
nal program memory. In addition to 256 x8 bits of on-chip  
RAM, up to 64 KByte of external RAM can be addressed.  
The flash memory blocks can be programmed via a stan-  
dard 87C5x OTP EPROM programmer fitted with a spe-  
cial adapter and the firmware for SST’s devices. During  
power-on reset, the devices can be configured as either  
a slave to an external host for source code storage or a  
master to an external host for an in-application program-  
ming (IAP) operation. The devices are designed to be  
programmed in-system and in-application on the printed  
circuit board for maximum flexibility. The devices are pre-  
programmed with an example of the bootstrap loader in  
the memory, demonstrating the initial user program code  
loading or subsequent user code updating via the IAP  
operation. The sample bootstrap loader is available for  
the user’s reference and convenience only; SST does not  
guarantee its functionality or usefulness. Chip-Erase or  
Block-Erase operations will erase the pre-programmed  
sample code.  
The devices come with 20/36 KByte of on-chip flash  
EEPROM program memory which is partitioned into 2  
independent program memory blocks. The primary  
Block 0 occupies 16/32 KByte of internal program mem-  
ory space and the secondary Block 1 occupies 4 KByte  
of internal program memory space.  
The 4 KByte secondary block can be mapped to the  
highest or lowest location of the 64 KByte address space;  
it can also be hidden from the program counter and used  
as an independent EEPROM-like data memory.  
©2004 Silicon Storage Technology, Inc.  
The SST logo, SuperFlash, and FlashFlex are registered trademarks of Silicon Storage Technology, Inc.  
These specifications are subject to change without notice.  
S71131-04-000  
1
6/04  

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