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SST39LF802C-55-4C-MAQE

更新时间： 2024-11-20 05:55:07
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器
页数 文件大小 规格书
38页 371K
描述
512K X 16 FLASH 2.7V PROM, 55 ns, PBGA48, 4 X 6 MM, 0.50 MM PITCH, ROHS COMPLIANT, MO-207CB-4, WFBGA-48

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SST39LF802C-55-4C-MAQE 数据手册

 浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第2页浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第3页浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第4页浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第5页浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第6页浏览型号SST39LF802C-55-4C-MAQE的Datasheet PDF文件第7页 
8 Mbit (x16) Multi-Purpose Flash Plus  
SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C  
A Microchip Technology Company  
Data Sheet  
The SST39VF801C / SST39VF802C / SST39LF801C / SST39LF802C are 512K  
x16 CMOS Multi-Purpose Flash Plus (MPF+) manufactured with SST proprietary,  
high performance CMOS SuperFlash® technology. The split-gate cell design and  
thick-oxide tunneling injector attain better reliability and manufacturability com-  
pared with alternate approaches. The SST39VF801C / SST39VF802C /  
SST39LF801C / SST39LF802C write (Program or Erase) with a 2.7-3.6V power  
supply. These devices conforms to JEDEC standard pinouts for x16 memories.  
Features  
• Organized as 512K x16  
• Security-ID Feature  
– SST: 128 bits; User: 128 words  
• Single Voltage Read and Write Operations  
• Fast Read Access Time:  
– 2.7-3.6V for SST39VF801C/802C  
– 3.0-3.6V for SST39LF801C/802C  
– 70 ns for SST39VF801C/802C  
– 55 ns for SST39LF801C/802C  
• Superior Reliability  
• Fast Erase and Word-Program:  
– Endurance: 100,000 Cycles (Typical)  
– Greater than 100 years Data Retention  
– Sector-Erase Time: 18 ms (typical)  
– Block-Erase Time: 18 ms (typical)  
– Chip-Erase Time: 40 ms (typical)  
– Word-Program Time: 7 µs (typical)  
• Low Power Consumption (typical values at 5 MHz)  
– Active Current: 5 mA (typical)  
– Standby Current: 3 µA (typical)  
– Auto Low Power Mode: 3 µA (typical)  
• Automatic Write Timing  
– Internal VPP Generation  
• Hardware Block-Protection/WP# Input Pin  
• End-of-Write Detection  
– Top Block-Protection (top 8 KWord)  
– Bottom Block-Protection (bottom 8 KWord)  
– Toggle Bits  
– Data# Polling  
– Ready/Busy# Pin  
• Sector-Erase Capability  
– Uniform 2 KWord sectors  
• CMOS I/O Compatibility  
• Block-Erase Capability  
• JEDEC Standard  
– Flexible block architecture; one 8-, two 4-, one 16-, and  
fifteen 32-KWord blocks  
– Flash EEPROM Pinouts and command sets  
• Chip-Erase Capability  
• Packages Available  
– 48-lead TSOP (12mm x 20mm)  
– 48-ball TFBGA (6mm x 8mm)  
– 48-ball WFBGA (4mm x 6mm)  
• Erase-Suspend/Erase-Resume Capabilities  
• Hardware Reset Pin (RST#)  
• Latched Address and Data  
• All devices are RoHS compliant  
www.microchip.com  
©2011 Silicon Storage Technology, Inc.  
DS25041A  
05/11  
1234567...38

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