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SST39LH512-45-4C-NH PDF预览

SST39LH512-45-4C-NH

更新时间： 2024-11-19 20:03:07
品牌 Logo 应用领域
芯科 - SILICON 内存集成电路
页数 文件大小 规格书
24页 224K
描述
Flash, 64KX8, 45ns, PQCC32

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中文翻译

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SST39LH512-45-4C-NH 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
包装说明：QCCJ, LDCC32,.5X.6Reach Compliance Code：unknown
风险等级：5.92最长访问时间：45 ns
命令用户界面：YES数据轮询：YES
JESD-30 代码：R-PQCC-J32JESD-609代码：e0
内存密度：524288 bit内存集成电路类型：FLASH
内存宽度：8部门数/规模：16
端子数量：32字数：65536 words
字数代码：64000最高工作温度：70 °C
最低工作温度：组织：64KX8
封装主体材料：PLASTIC/EPOXY封装代码：QCCJ
封装等效代码：LDCC32,.5X.6封装形状：RECTANGULAR
封装形式：CHIP CARRIER并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
部门规模：4K最大待机电流：0.000015 A
子类别：Flash Memories最大压摆率：0.015 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：J BEND
端子节距：1.27 mm端子位置：QUAD
切换位：YES类型：NOR TYPE
Base Number Matches：1

SST39LH512-45-4C-NH 数据手册

 浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第2页浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第3页浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第4页浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第5页浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第6页浏览型号SST39LH512-45-4C-NH的Datasheet PDF文件第7页 
512 Kbit / 1 Mbit / 2 Mbit / 4 Mbit High Speed Multi-Purpose Flash  
SST39LH512 / SST39LH010 / SST39LH020 / SST39LH040  
Advance Information  
FEATURES:  
•
•
•
Organized as 64K x8/ 128K x8/ 256K x8/ 512K x8  
Single 3.0-3.6V Read and Write Operations  
Superior Reliability  
•
Fast Sector Erase and Byte Program:  
1
– Sector Erase Time: 18 ms typical  
– Chip Erase Time: 70 ms typical  
– Byte Program time: 14 µs typical  
– Chip Rewrite Time:  
– Endurance: 100,000 Cycles (typical)  
– Greater than 100 years Data Retention  
2
1 second typical for SST39LH512  
2 seconds typical for SST39LH010  
4 seconds typical for SST39LH020  
8 seconds typical for SST39LH040  
•
Low Power Consumption:  
– Active Current: 10 mA (typical)  
– Standby Current: 10 µA (typical)  
3
•
•
Automatic Write Timing  
– Internal Vpp Generation  
End of Write Detection  
•
•
Sector Erase Capability  
– Uniform 4 KByte sectors  
Fast Read Access Time:  
4
– Toggle Bit  
– Data# Polling  
– 45 and 55 ns for SST39LH512 / SST39LH010  
– 55 ns for SST39LH512 / SST39LH010 /  
SST39LH020 / SST39LH040  
5
•
•
CMOS I/O Compatibility  
JEDEC Standard  
•
Latched Address and Data  
6
– Flash EEPROM Pinouts and command sets  
Packages Available  
•
– 32-Pin PLCC  
– 32-Pin TSOP (8mm x 14mm)  
7
PRODUCT DESCRIPTION  
nologies. The total energy consumed is a function of the  
applied voltage, current, and time of application. Since  
for any given voltage range, the SuperFlash technology  
uses less current to program and has a shorter erase  
time, the total energy consumed during any Erase or  
Program operation is less than alternative flash tech-  
nologies. The SST39LHxxx device also improves flex-  
ibility while lowering the cost for program, data, and  
configuration storage applications.  
8
The SST39LHxxx is a CMOS Multi-Purpose Flash  
(MPF)manufacturedwithSST’sproprietary,highperfor-  
mance CMOS SuperFlash technology. The split-gate  
celldesignandthickoxidetunnelinginjectorattainbetter  
reliabilityandmanufacturabilitycomparedwithalternate  
approaches. The SST39LHxxx device writes (Program  
or Erase) with a 3.0-3.6V power supply. The  
SST39LHxxx device conforms to JEDEC standard  
pinouts for x8 memories.  
9
10  
11  
12  
13  
14  
15  
16  
The SuperFlash technology provides fixed Erase and  
Program times, independent of the number of Erase/  
Program cycles that have occurred. Therefore the sys-  
tem software or hardware does not have to be modified  
or de-rated as is necessary with alternative flash tech-  
nologies, whose erase and program times increase with  
accumulated Erase/Program cycles.  
Featuring high performance byte program, the  
SST39LHxxxdeviceprovidesamaximumbyte-program  
time of 20 µsec. The device uses Toggle Bit or Data#  
Polling to detect the completion of Program or Erase  
operations. To protect against inadvertent write, the  
SST39LHxxxdevicehason-chiphardwareandsoftware  
dataprotectionschemes. Designed, manufactured, and  
tested for a wide spectrum of applications, the  
SST39LHxxxdeviceisofferedwithaguaranteedendur-  
ance of 10,000 cycles. Data retention is rated at greater  
than 100 years.  
To meet high density, surface mount requirements, the  
SST39LHxxx device is offered in 32-pin TSOP and 32-  
pin PLCC packages. See Figures 1 and 2 for pinouts.  
Device Operation  
Commands are used to initiate the memory operation  
functions of the device. Commands are issued to the  
deviceusingstandardmicroprocessorwritesequences.  
A command is loaded by asserting WE# low while  
keeping CE# low. The address bus is latched on the  
falling edge of WE# or CE#, whichever occurs last. The  
data bus is latched on the rising edge of WE# or CE#,  
whichever occurs first.  
The SST39LHxxx device is suited for applications that  
requireconvenientandeconomicalupdatingofprogram,  
configuration, or data memory. For all system applica-  
tions, the SST39LHxxx device significantly improves  
performance and reliability, while lowering power con-  
sumption.TheSST39LHxxxinherentlyuseslessenergy  
during erase and program than alternative flash tech-  
© 1999 Silicon Storage Technology, Inc.The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc. MPF is a trademark of Silicon Storage Technology, Inc.  
351-04 5/99 These specifications are subject to change without notice.  
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