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SST27SF010-90-3C-PHE

更新时间： 2024-11-01 14:31:15
品牌 Logo 应用领域
美国微芯 - MICROCHIP 可编程只读存储器光电二极管内存集成电路
页数 文件大小 规格书
23页 253K
描述
128K X 8 FLASH 12V PROM, 90 ns, PDIP28, LEAD FREE, PLASTIC, MO-015AH, DIP-28

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SST27SF010-90-3C-PHE 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：DIP
包装说明：DIP,针数：28
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.32.00.51风险等级：5.73
最长访问时间：90 nsJESD-30 代码：R-PDIP-T28
JESD-609代码：e3长度：41.91 mm
内存密度：1048576 bit内存集成电路类型：FLASH
内存宽度：8功能数量：1
端子数量：28字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE并行/串行：PARALLEL
峰值回流温度（摄氏度）：260编程电压：12 V
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子面层：MATTE TIN端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：40类型：NOR TYPE
宽度：15.24 mmBase Number Matches：1

SST27SF010-90-3C-PHE 数据手册

 浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第2页浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第3页浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第4页浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第5页浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第6页浏览型号SST27SF010-90-3C-PHE的Datasheet PDF文件第7页 
512 Kbit / 1 Mbit / 2 Mbit (x8) Many-Time Programmable Flash  
SST27SF512 / SST27SF010 / SST27SF020  
SST27SF512 / 010 / 0205.0V-Read 512Kb / 1Mb / 2Mb (x8) MTP flash memories  
Data Sheet  
FEATURES:  
•
•
•
Organized as 64K x8 / 128K x8 / 256K x8  
4.5-5.5V Read Operation  
•
Fast Byte-Program Operation  
– Byte-Program Time: 20 µs (typical)  
– Chip Program Time:  
Superior Reliability  
1.4 seconds (typical) for SST27SF512  
2.8 seconds (typical) for SST27SF010  
5.6 seconds (typical) for SST27SF020  
– Endurance: At least 1000 Cycles  
– Greater than 100 years Data Retention  
•
•
Low Power Consumption  
•
Electrical Erase Using Programmer  
– Active Current: 20 mA (typical)  
– Standby Current: 10 µA (typical)  
– Does not require UV source  
– Chip-Erase Time: 100 ms (typical)  
Fast Read Access Time  
•
•
•
TTL I/O Compatibility  
– 70 ns  
– 90 ns  
JEDEC Standard Byte-wide EPROM Pinouts  
Packages Available  
– 32-lead PLCC  
– 32-lead TSOP (8mm x 14mm)  
– 28-pin PDIP for SST27SF512  
– 32-pin PDIP for SST27SF010/020  
PRODUCT DESCRIPTION  
The SST27SF512/010/020 are a 64K x8 / 128K x8 / 256K  
x8 CMOS, Many-Time Programmable (MTP) low cost  
flash, manufactured with SST’s proprietary, high perfor-  
mance SuperFlash technology. The split-gate cell design  
and thick oxide tunneling injector attain better reliability and  
manufacturability compared with alternate approaches.  
These MTP devices can be electrically erased and pro-  
grammed at least 1000 times using an external program-  
mer with a 12V power supply. They have to be erased prior  
to programming. These devices conform to JEDEC stan-  
dard pinouts for byte-wide memories.  
Device Operation  
The SST27SF512/010/020 are a low cost flash solution  
that can be used to replace existing UV-EPROM, OTP,  
and mask ROM sockets. These devices are functionally  
(read and program) and pin compatible with industry  
standard EPROM products. In addition to EPROM func-  
tionality, these devices also support electrical Erase  
operation via an external programmer. They do not  
require a UV source to erase, and therefore the pack-  
ages do not have a window.  
Featuring high performance Byte-Program, the  
SST27SF512/010/020 provide a Byte-Program time of 20  
µs. Designed, manufactured, and tested for a wide spec-  
trum of applications, these devices are offered with an  
endurance of at least 1000 cycles. Data retention is rated at  
greater than 100 years.  
Read  
The Read operation of the SST27SF512/010/020 is con-  
trolled by CE# and OE#. Both CE# and OE# have to be low  
for the system to obtain data from the outputs. Once the  
address is stable, the address access time is equal to the  
delay from CE# to output (TCE). Data is available at the out-  
put after a delay of TOE from the falling edge of OE#,  
assuming that CE# pin has been low and the addresses  
have been stable for at least TCE-TOE. When the CE# pin is  
high, the chip is deselected and a typical standby current of  
10 µA is consumed. OE# is the output control and is used  
to gate data from the output pins. The data bus is in high  
impedance state when either CE# or OE# is high.  
The SST27SF512/010/020 are suited for applications that  
require infrequent writes and low power nonvolatile stor-  
age. These devices will improve flexibility, efficiency, and  
performance while matching the low cost in nonvolatile  
applications that currently use UV-EPROMs, OTPs, and  
mask ROMs.  
To meet surface mount and conventional through hole  
requirements, the SST27SF512 are offered in 32-lead  
PLCC, 32-lead TSOP, and 28-pin PDIP packages. The  
SST27SF010/020 are offered in 32-pin PDIP, 32-lead  
PLCC, and 32-lead TSOP packages. See Figures 1, 2, and  
3 for pin assignments.  
©2004 Silicon Storage Technology, Inc.  
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.  
MTP is a trademark of Silicon Storage Technology, Inc.  
S71152-08-000  
1
4/04  
These specifications are subject to change without notice.  
1234567...23

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SST27SF010-90-3C-PHE 替代型号

型号 品牌 替代类型 描述 数据表
TC531000CP TOSHIBA

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