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SPQ1R9N40WP PDF预览

SPQ1R9N40WP

更新时间: 2024-11-21 17:15:47
品牌 Logo 应用领域
中科君芯 - CAS-JUNSHINE /
页数 文件大小 规格书
3页 297K
描述
LV-SGT

SPQ1R9N40WP 数据手册

 浏览型号SPQ1R9N40WP的Datasheet PDF文件第2页浏览型号SPQ1R9N40WP的Datasheet PDF文件第3页 
SPQ1R9N40WP  
SYMBOL  
40V, 80A (1) N-Channel MOSFET  
Proprietary Trench Gate Device Design and Processes  
High Reliability Capability  
Drain  
Sampled CP Probing and Inking  
Gate  
Source  
Electrical Characteristics in C/P Test (TJ at 25 )  
Symbol  
V(BR)DSS  
RDS(ON)  
RDS(ON)  
VGS (th)  
IDSS  
Parameter  
Min. Typ. Max. Unit  
Test Condition  
Drain-Source Breakdown Voltage  
Static Drain-Source On-Resistance  
Static Drain-Source On-Resistance  
Gate Threshold Voltage  
40  
1
1.4  
2.6  
1.9  
4
V
VGS =0V, ID =250µA  
(2)  
(2)  
mΩ  
mΩ  
V
VGS =10V, ID =1A  
VGS =4.5V, ID =1A  
VDS =VGS, ID =250µA  
VDS =32V, VGS =0V  
VDS =0V, VGS =±20V  
2.5  
1
µ
A
Drain-to-Source Leakage Current  
Gate-Body Leakage Current  
IGSS  
±100  
nA  
TJ, TSTG  
Operating and Storage Temperature  
-55to 150Max.  
Mechanical Data  
Die Drawing  
1600 µ  
µ
µ
Chip Size  
m X 2539 m  
µ
Gate Pad Size  
Source Pad Size  
Scribe Line Width  
Wafer Thickness  
Wafer Diameter  
Gross Die  
140 m X 135 m  
µ
µ
1400 m X 2339 m  
µ
60 m  
µ
150 m  
200 mm  
6584 EA  
µ
Source Metallization  
Drain Metallization  
Passivation  
Al-Cu (4 m typical)  
Ti-Ni-Ag  
Yes  
Recommended Storage  
Environment  
Store in original container, in dry nitrogen, 6  
months at ambient temperature of 23°C ± 3°C  
(1) This characteristic assumes the die is assembled in SOP-8 package. Actual performance may degrade when  
assembled.  
(2) Pulse Width tp = < 1 mS, Duty Cycle < 2%.  
Address: Floor 5, C1 Building, No. 200, Linghu Blvd., Wuxi, Jiangshu, China  
Version: Preliminary Rev 0.2  
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1 ̶  

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