Datasheet > SPQ3R8N30WPIL

SPQ3R8N30WPIL

更新时间： 2024-09-24 17:15:35

品牌	Logo	应用领域
中科君芯 - CAS-JUNSHINE		/
页数	文件大小	规格书
3页	323K
描述
LV-SGT

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SPQ3R8N30WPIL 数据手册

SPQ3R8N30WPIL

30V, 33A ⁽¹⁾N-Channel MOSFET

● Proprietary Trench Gate Device Design and Processes

● High Reliability Capability

SYMBOL

Drain

● Sampled CP Probing and Inking

Gate

Source

℃

Electrical Characteristics in C/P Test (T_Jat 25 )

Symbol

V_(BR)DSS

R_DS(ON)

V_{GS (th)}

I_DSS

Parameter

Min. Typ. Max. Unit

Test Condition

Drain-Source Breakdown Voltage

Static Drain-Source On-Resistance

Gate Threshold Voltage

—

3.8

mΩ

V_GS=0V, I_D=250µA

(2)

V_GS=4.5V, I_D=1A

—

V_DS=V_GS, I_D=250µA

Drain-to-Source Leakage Current

Gate-Body Leakage Current

Operating and Storage Temperature

—

V_DS=24V, V_GS=0V

V_DS=0V, V_GS=±20V

I_GSS

±100

T_J, T_STG

-55℃ to 150℃ Max.

Mechanical Data

Die Drawing

1496 µ

Chip Size

m X 1885 m

Gate Pad Size

160 m X 80 m

Source Pad Size(1)(2)

Source Pad Size(3)(4)

Scribe Line Width

Wafer Thickness

Wafer Diameter

Gross Die

468 m X 1056 m

60 m

100 m

200 mm

10231 EA

Source Metallization

Drain Metallization

Passivation

Ni-Pb-Au (1KA/3KA/1.5KA typical)

Ti-Ni-Ag

Polyimide

Recommended Storage

Environment

Store in original container, in dry nitrogen, 6

months at ambient temperature of 23°C ± 3°C

(1) This characteristic assumes the die is assembled in DFN5*6 package. Actual performance may degrade when

assembled.

(2) Pulse Width tp = < 1 mS, Duty Cycle < 2%.

Address: Floor 5, C1 Building, No. 200, Linghu Blvd., Wuxi, Jiangshu, China

Version: Preliminary Rev 0.0

1 ̶

12 3

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