Datasheet > SPC5707BEVLUR

SPC5707BEVLUR

更新时间： 2024-10-29 06:13:19

品牌	Logo	应用领域
飞思卡尔 - FREESCALE		微控制器
页数	文件大小	规格书
92页	1073K
描述
Microcontroller

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

SPC5707BEVLUR 数据手册

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5607B

Rev. 3, 01/2010

MPC5607B

MPC5607B Microcontroller

Data Sheet

208 MAPBGA (17 x 17

)

100 LQFP (14 x 14 )

144 LQFP (20 x 20 )

176LQFP (24 x 24)

Features

•

Up to 6 serial peripheral interface (DSPI) modules

Up to 10 serial communication interface (LINFlex)

modules

•

Single issue, 32-bit CPU core complex (e200z0h)

— Compliant with the Power Architecture™

embedded category

•

Up to 6 enhanced full CAN (FlexCAN) modules

with configurable buffers

— Enhanced instruction set allowing variable

length encoding (VLE) for code size footprint

reduction. With the optional encoding of mixed

16-bit and 32-bit instructions, it is possible to

achieve significant code size footprint

reduction.

•

1 inter-integrated circuit (I C) interface module

Up to 149 configurable general purpose pins

supporting input and output operations (package

dependent)

•

Real-Time Counter (RTC)

•

Up to 1.5 Mbytes on-chip Flash supported with the

Flash controller

— Clock source from internal 128 kHz or 16 MHz

oscillator supporting autonomous wakeup with

1 ms resolution with maximum timeout of 2

seconds

•

Up to 96 Kbytes on-chip SRAM

Memory protection unit (MPU) with 8 region

descriptors and 32-byte region granularity on certain

family members

— Optional support for RTC with clock source

from external 32 kHz crystal oscillator,

supporting wakeup with 1 sec resolution and

maximum timeout of 1 hour

•

Interrupt controller (INTC) capable of handling 204

selectable-priority interrupt sources

•

Up to 8 periodic interrupt timers (PIT) with 32-bit

counter resolution

•

Frequency modulated phase-locked loop (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, Flash, or RAM from multiple bus

masters

Nexus development interface (NDI) per IEEE-ISTO

5001-2003 Class Two Plus

Device/board boundary scan testing supported per

Joint Test Action Group (JTAG) of IEEE (IEEE

1149.1)

•

16-channel eDMA controller with multiple transfer

request sources using DMA multiplexer

Boot assist module (BAM) supports internal Flash

programming via a serial link (CAN or SCI)

•

On-chip voltage regulator (VREG) for regulation of

input supply for all internal levels

Timer supports I/O channels providing a range of

16-bit input capture, output compare, and pulse

width modulation functions (eMIOS)

•

2 analog-to-digital converters (ADC): one 10-bit and

one 12-bit

Cross Trigger Unit to enable synchronization of

ADC conversions with a timer event from the

eMIOS or PIT

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Preliminary—Subject to Change Without Notice

12 3 4 5 6 7...92

中文翻译

下载PDF

与SPC5707BEVLUR相关器件

型号	品牌	获取价格	描述	数据表
SPC5707CECLLR	FREESCALE	获取价格	Microcontroller
SPC5707CECLQR	FREESCALE	获取价格	Microcontroller
SPC5707CECLUR	FREESCALE	获取价格	Microcontroller
SPC5707CEMLLR	FREESCALE	获取价格	Microcontroller
SPC5707CEMLQR	FREESCALE	获取价格	Microcontroller
SPC5707CEMLUR	FREESCALE	获取价格	Microcontroller
SPC5707CEVLLR	FREESCALE	获取价格	Microcontroller
SPC5707CEVLQR	FREESCALE	获取价格	Microcontroller
SPC5707CEVLUR	FREESCALE	获取价格	Microcontroller
SPC570S40E1	STMICROELECTRONICS	获取价格	Single issue 4-stage pipeline in-order execution core

与SPC5707BEVLUR相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

15
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

17
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

41
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

49

产品中心

服务支持

精选活动

关于我们

帮助中心

SPC5707BEVLUR

SPC5707BEVLUR 数据手册

与SPC5707BEVLUR相关器件

与SPC5707BEVLUR相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

SPC5707BEVLUR

SPC5707BEVLUR 数据手册

与SPC5707BEVLUR相关器件

与SPC5707BEVLUR相关文章

您还可以找

您在本页遇到什么问题？