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SPC5707CEVLQR PDF预览

SPC5707CEVLQR

更新时间： 2024-10-29 06:13:19
品牌 Logo 应用领域
飞思卡尔 - FREESCALE 微控制器
页数 文件大小 规格书
92页 1073K
描述
Microcontroller

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SPC5707CEVLQR 数据手册

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Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5607B  
Rev. 3, 01/2010  
MPC5607B  
MPC5607B Microcontroller  
Data Sheet  
208 MAPBGA (17 x 17  
)
100 LQFP (14 x 14 )  
144 LQFP (20 x 20 )  
176LQFP (24 x 24)  
Features  
•
•
Up to 6 serial peripheral interface (DSPI) modules  
Up to 10 serial communication interface (LINFlex)  
modules  
•
Single issue, 32-bit CPU core complex (e200z0h)  
— Compliant with the Power Architecture™  
embedded category  
•
Up to 6 enhanced full CAN (FlexCAN) modules  
with configurable buffers  
— Enhanced instruction set allowing variable  
length encoding (VLE) for code size footprint  
reduction. With the optional encoding of mixed  
16-bit and 32-bit instructions, it is possible to  
achieve significant code size footprint  
reduction.  
2
•
•
1 inter-integrated circuit (I C) interface module  
Up to 149 configurable general purpose pins  
supporting input and output operations (package  
dependent)  
•
Real-Time Counter (RTC)  
•
Up to 1.5 Mbytes on-chip Flash supported with the  
Flash controller  
— Clock source from internal 128 kHz or 16 MHz  
oscillator supporting autonomous wakeup with  
1 ms resolution with maximum timeout of 2  
seconds  
•
•
Up to 96 Kbytes on-chip SRAM  
Memory protection unit (MPU) with 8 region  
descriptors and 32-byte region granularity on certain  
family members  
— Optional support for RTC with clock source  
from external 32 kHz crystal oscillator,  
supporting wakeup with 1 sec resolution and  
maximum timeout of 1 hour  
•
Interrupt controller (INTC) capable of handling 204  
selectable-priority interrupt sources  
•
•
•
Up to 8 periodic interrupt timers (PIT) with 32-bit  
counter resolution  
•
•
Frequency modulated phase-locked loop (FMPLL)  
Crossbar switch architecture for concurrent access to  
peripherals, Flash, or RAM from multiple bus  
masters  
Nexus development interface (NDI) per IEEE-ISTO  
5001-2003 Class Two Plus  
Device/board boundary scan testing supported per  
Joint Test Action Group (JTAG) of IEEE (IEEE  
1149.1)  
•
•
•
16-channel eDMA controller with multiple transfer  
request sources using DMA multiplexer  
Boot assist module (BAM) supports internal Flash  
programming via a serial link (CAN or SCI)  
•
On-chip voltage regulator (VREG) for regulation of  
input supply for all internal levels  
Timer supports I/O channels providing a range of  
16-bit input capture, output compare, and pulse  
width modulation functions (eMIOS)  
•
•
2 analog-to-digital converters (ADC): one 10-bit and  
one 12-bit  
Cross Trigger Unit to enable synchronization of  
ADC conversions with a timer event from the  
eMIOS or PIT  
This document contains information on a product under development. Freescale reserves the  
right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2010. All rights reserved.  
Preliminary—Subject to Change Without Notice  
1234567...92

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