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SPC570S40E3 PDF预览

SPC570S40E3

更新时间: 2024-10-30 01:09:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
68页 1246K
描述
Single issue 4-stage pipeline in-order execution core

SPC570S40E3 数据手册

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SPC570S40E1, SPC570S40E3,  
SPC570S50E1, SPC570S50E3  
32-bit Power Architecture® microcontroller for automotive ASILD  
applications  
Datasheet - production data  
– Check of safety mechanisms availability  
and error reaction path functionality by  
dedicated mechanisms  
– Safety of the periphery by application-level  
eTQFP64 (10 x 10 x 1.0 mm)  
eTQFP100 (14 x 14 x 1.0 mm)  
measures supported by replicated  
peripheral bridges and by LBIST  
– Further measures on dedicated peripherals  
(e.g. ADC supervisor)  
Features  
High performance e200z0h dual core  
– 32-bit Power Architecture technology CPU  
– Core frequency as high as 80 MHz  
– Junction temperature sensor  
– 8-region system memory protection unit  
(SMPU) with process ID support (tasks  
isolation)  
– Single issue 4-stage pipeline in-order  
execution core  
– Enhanced SW watchdog  
– Variable Length Encoding (VLE)  
– Cyclic redundancy check (CRC) unit  
Up to 544 KB (512 KB code + 32 KB data,  
suitable for EEPROM emulation) on-chip flash  
memory: supports read during program and  
erase operations, and multiple blocks allowing  
EEPROM emulation  
Dual phase-locked loops with stable clock  
domain for peripherals and FM modulation  
domain for computational shell  
Nexus Class 3 debug and trace interface  
Up to 48 KB on-chip general-purpose SRAM  
Communication interfaces  
Multi-channel direct memory access controller  
– 2 LINFlexD modules  
– 3 deserial serial peripheral interface (DSPI)  
modules  
– Up to 2 FlexCAN interfaces with 32  
message buffers each  
(eDMA paired in lockstep) with 16 channels  
Comprehensive new generation ASILD safety  
concept  
– Safety of bus masters (core+INTC, DMA)  
by delayed lockstep approach  
– Safety of storage (Flash, SRAM) by mainly  
ECC  
On-chip CAN/UART Bootstrap loader with Boot  
Assisted Flash (BAF). Physical Interface (PHY)  
can be  
– Safety of the data path to storage and  
periphery by mainly End-to-End EDC (E2E  
EDC)  
– Clock and power, generation and  
distribution, supervised by dedicated  
monitors  
– Fault Collection and Control Unit (FCCU)  
for collection and reaction to failure  
notifications  
– UART  
– CAN  
2 enhanced 12-bit SAR analog converters  
– 1.5 µs conversion time (12 MHz)  
– 16 physical channels (fully shared between  
the 2 SARADC units)  
– Supervisor ADC concept  
– Programmable Cross Triggering Unit (CTU)  
Single 3.3 V or 5 V voltage supply  
– Memory Error Management Unit (MEMU)  
for collection and reporting of error events  
in memories  
4 general purpose eTimer units (6 channels  
each)  
– Boot time MBIST and LBIST for latent  
faults  
Junction temperature range -40 °C to 150 °C  
September 2015  
DocID024492 Rev 6  
1/68  
This is information on a product in full production.  
www.st.com  

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