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SPC56EL60L5CBOSY PDF预览

SPC56EL60L5CBOSY

更新时间: 2024-10-29 17:33:19
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意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
160页 1248K
描述
用于汽车底盘和安全应用的32位Power Architecture MCU

SPC56EL60L5CBOSY 数据手册

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SPC56EL60x, SPC56EL54x  
SPC564L60x, SPC564L54x  
32-bit Power Architecture® microcontroller for automotive  
SIL3/ASILD chassis and safety applications  
Datasheet production data  
Features  
High-performance e200z4d dual core  
®
– 32-bit Power Architecture technology CPU  
– Core frequency as high as 120 MHz  
– Dual issue five-stage pipeline core  
– Variable Length Encoding (VLE)  
– Memory Management Unit (MMU)  
LQFP100 (14 x 14x 1.4 mm)  
LQFP144 (20 x 20 x 1.4 mm)  
Decoupled Parallel mode for high-performance  
– 4 KB instruction cache with error detection  
code  
use of replicated cores  
– Signal processing engine (SPE)  
Nexus Class 3+ interface  
Memory available  
Interrupts  
– Up to 1 MB flash memory with ECC  
– Up to 128 KB on-chip SRAM with ECC  
– Replicated 16-priority controller  
– Replicated 16-channel eDMA controller  
– Built-in RWW capabilities for EEPROM  
emulation  
GPIOs individually programmable as input,  
output or special function  
SIL3/ASILD innovative safety concept:  
Three 6-channel general-purpose eTimer units  
LockStep mode and Fail-safe protection  
2 FlexPWM units  
– Sphere of replication (SoR) for key  
components (such as CPU core, eDMA,  
crossbar switch)  
– Four 16-bit channels per module  
Communications interfaces  
– 2 LINFlexD channels  
– Fault collection and control unit (FCCU)  
– 3 DSPI channels with automatic chip select  
generation  
– 2 FlexCAN interfaces (2.0B Active) with 32  
message objects  
– Redundancy control and checker unit  
(RCCU) on outputs of the SoR connected  
to FCCU  
– Boot-time Built-In Self-Test for Memory  
(MBIST) and Logic (LBIST) triggered by  
hardware  
– FlexRay module (V2.1 Rev. A) with 2  
channels, 64 message buffers and data  
rates up to 10 Mbit/s  
– Boot-time Built-In Self-Test for ADC and  
flash memory triggered by software  
Two 12-bit analog-to-digital converters (ADCs)  
– Replicated safety enhanced watchdog  
– Replicated junction temperature sensor  
– Non-maskable interrupt (NMI)  
– 16 input channels  
– Programmable cross triggering unit (CTU)  
to synchronize ADCs conversion with timer  
and PWM  
– 16-region memory protection unit (MPU)  
– Clock monitoring units (CMU)  
– Power management unit (PMU)  
Sine wave generator (D/A with low pass filter)  
On-chip CAN/UART bootstrap loader  
– Cyclic redundancy check (CRC) unit  
Single 3.0 V to 3.6 V voltage supply  
Ambient temperature range –40 °C to 125 °C  
Junction temperature range –40 °C to 150 °C  
August 2012  
Doc ID 15457 Rev 8  
1/160  
This is information on a product in full production.  
www.st.com  
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