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SPC56EL70L3CBFSR PDF预览

SPC56EL70L3CBFSR

更新时间: 2024-11-25 17:33:19
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS /
页数 文件大小 规格书
128页 2371K
描述
用于汽车底盘和安全应用的32位Power Architecture MCU

SPC56EL70L3CBFSR 数据手册

 浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第2页浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第3页浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第4页浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第5页浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第6页浏览型号SPC56EL70L3CBFSR的Datasheet PDF文件第7页 
SPC56EL70L3, SPC56EL70L5,  
SPC564L70L3, SPC564L70L5  
32-bit Power Architecture®microcontroller for automotive  
SIL3/ASILD chassis and safety applications  
Datasheet - production data  
– Replicated junction temperature sensor  
– Non Maskable Interrupt (NMI)  
– 16-region Memory Protection Unit (MPU)  
– Clock Monitoring Units (CMU)  
– Power Management Unit (PMU)  
– Cyclic Redundancy Check (CRC) unit  
LQFP100 (14 x 14x 1.4 mm)  
LQFP144 (20 x 20 x 1.4 mm)  
Decoupled Parallel mode for high performance  
use of replicated cores  
Features  
Nexus Class 3+ interface  
Interrupts  
High-performance e200z4d dual core  
®
– Replicated 16-priority controller  
– Replicated 16-channel eDMA controller  
– 32-bit Power Architecture technology  
CPU  
– Core frequency as high as 120 MHz  
– Dual issue five-stage pipeline core  
– Variable Length Encoding (VLE)  
– Memory Management Unit (MMU)  
GPIOs individually programmable as input,  
output or special function  
Three 6-channel general-purpose eTimer units  
2 FlexPWM units: Four 16-bit channels per  
– 4 KB instruction cache with error detection  
code  
module  
Communications interfaces  
– Signal Processing Engine (SPE)  
– 2 LINFlexD channels  
Memory available  
– 3 DSPI channels with automatic chip select  
generation  
– 2 MB flash memory with ECC  
– 192 KB on-chip SRAM with ECC  
– 3 FlexCAN interfaces (2.0B Active) with 32  
message objects  
– Built-in RWW capabilities for EEPROM  
emulation  
– FlexRay module (V2.1 Rev. A) with 2  
channels, 64 message buffers and data  
rates up to 10 Mbit/s  
SIL3/ASILD innovative safety concept: Lock  
step mode and Fail-safe protection  
– Sphere of Replication (SoR) for key  
components (such as CPU core, eDMA,  
crossbar switch)  
Two 12-bit Analog-to-digital Converters (ADC)  
– 16 input channels  
– Programmable Cross Triggering Unit (CTU)  
to synchronize ADCs conversion with timer  
and PWM  
– Fault Collection and Control Unit (FCCU)  
– Redundancy Control and Checker Unit  
(RCCU) on outputs of the SoR connected  
to FCCU  
Sine wave generator (D/A with low pass filter)  
On-chip CAN/UART/FlexRay Bootstrap loader  
Single 3.0 V to 3.6 V voltage supply  
– Boot-time Built-In Self-Test for Memory  
(MBIST) and Logic (LBIST) triggered by  
hardware  
Ambient temperature range –40 °C to 125 °C  
Junction temperature range –40 °C to 150 °C  
– Boot-time Built-In Self-Test for ADC and  
flash memory triggered by software  
– Replicated safety enhanced watchdog  
July 2015  
DocID023953 Rev 5  
1/128  
This is information on a product in full production.  
www.st.com  

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