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SPC56AP54L5 PDF预览

SPC56AP54L5

更新时间: 2024-10-28 12:23:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 闪存
页数 文件大小 规格书
104页 1028K
描述
32-bit Power Architecture® based MCU with 1088 KB Flash memory and 80 KB RAM for automotive chassis and safety applications

SPC56AP54L5 数据手册

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SPC56AP60x, SPC56AP54x  
SPC560P60x, SPC560P54x  
32-bit Power Architecture® based MCU with 1088 KB Flash memory  
and 80 KB RAM for automotive chassis and safety applications  
Datasheet production data  
Features  
64 MHz, dual issue, 32-bit CPU core complex  
(e200z0h)  
– Compliant with Power Architecture  
LQFP100  
14 x 14 mm  
LQFP144  
20 x 20 mm  
®
embedded category  
Communications interfaces  
– Variable Length Encoding (VLE)  
– 2 LINFlex modules (LIN 2.1,  
Memory organizazion  
1 × Master/Slave, 1 × Master Only)  
– Up to 1024 KB on-chip code Flash memory  
– 5 DSPI modules with automatic chip select  
with additional 64 KB for EEPROM  
generation  
emulation (data flash), with ECC, with  
– 2 FlexCAN interfaces (2.0B Active) with 32  
erase/program controller  
message buffers  
– Up to 80 KB on-chip SRAM with ECC  
– 1 Safety port based on FlexCAN; usable as  
Fail safe protection  
third CAN when not used as safety port  
– ECC protection on system SRAM and  
Flash  
– Safety port  
– 1 FlexRay™ module (V2.1) with dual or  
single channel, 64 message buffers and up  
to 10 Mbit/s  
– SWT with servicing sequence pseudo-  
random generator  
– Power management  
2 CRC units with three contexts and 3  
hardwired polynomials(CRC8,CRC32 and  
CRC-16-CCITT)  
– Non-maskable interrupt for both cores  
– Fault collection and control unit (FCCU)  
– Safe mode of system-on-chip (SoC)  
– Register protection scheme  
10-bit A/D converter  
– 27 input channels and pre-sampling feature  
– Conversion time < 1 µs including sampling  
time at full precision  
Nexus® L2+ interface  
– Programmable cross triggering unit (CTU)  
– 4 analog watchdog with interrupt capability  
Single 3.3 V or 5 V supply for I/Os and ADC  
2 on-platform peripherals set with 2 INTC  
On-chip CAN/UART Bootstrap loader with boot  
assist module (BAM)  
16-channel eDMA controller with multiple  
Ambient temperature ranges: –40 to 125 °C or  
transfer request sources  
–40 to 105 °C  
General purpose I/Os (80 GPIO + 26 GPI on  
LQFP144; 49 GPIO + 16 GPI on LQFP100)  
Table 1.  
Package  
Device summary  
Part number  
2 general purpose eTimer units  
– 6 timers, each with up/down count  
capabilities  
768 KB Flash  
1 MB Flash  
– 16-bit resolution, cascadable counters  
– Quadrature decode with rotation direction  
flag  
SPC560P54L5  
SPC56AP54L5  
SPC560P60L5  
SPC56AP60L5  
LQFP144  
LQFP100  
SPC560P54L3  
SPC56AP54L3  
SPC560P60L3  
SPC56AP60L3  
– Double buffer input capture and output  
compare  
May 2012  
Doc ID 18340 Rev 3  
1/104  
This is information on a product in full production.  
www.st.com  
1
 

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