SPC56AP60x, SPC56AP54x
SPC560P60x, SPC560P54x
32-bit Power Architecture® based MCU with 1088KB Flash memory
and 80KB RAM for automotive chassis and safety applications
Datasheet - production data
General purpose I/Os (80 GPIO + 26 GPI on
LQFP144; 49 GPIO + 16 GPI on LQFP100)
2 general purpose eTimer units
– 6 timers, each with up/down count
LQFP100
14 x 14 mm
capabilities
LQFP144
20 x 20 mm
– 16-bit resolution, cascadable counters
– Quadrature decode with rotation direction
flag
Features
– Double buffer input capture and output
AEC-Q10x qualified
compare
64 MHz, single issue, 32-bit CPU core complex
Communications interfaces
(e200z0h)
– 2 LINFlex modules (LIN 2.1,
®
– Compliant with Power Architecture
1 × Master/Slave, 1 × Master Only)
embedded category
– 5 DSPI modules with automatic chip select
generation
– Variable Length Encoding (VLE)
Memory organization
– 2 FlexCAN interfaces (2.0B Active) with 32
message buffers
– Up to 1024 KB on-chip code Flash memory
with additional 64 KB for EEPROM
emulation (data flash), with ECC, with
erase/program controller
– 1 Safety port based on FlexCAN; usable as
third CAN when not used as safety port
– 1 FlexRay™ module (V2.1) with dual or
single channel, 64 message buffers and up
to 10 Mbit/s
– Up to 80 KB on-chip SRAM with ECC
Fail safe protection
2 CRC units with three contexts and 3
hardwired polynomials(CRC8,CRC32 and
CRC-16-CCITT)
– ECC protection on system SRAM and
Flash
– Safety port
10-bit A/D converter
– SWT with servicing sequence pseudo-
random generator
– 27 input channels and pre-sampling feature
– Conversion time < 1 µs including sampling
time at full precision
– Power management
– Non-maskable interrupt for both cores
– Fault collection and control unit (FCCU)
– Safe mode of system-on-chip (SoC)
– Register protection scheme
– Programmable cross triggering unit (CTU)
– 4 analog watchdog with interrupt capability
On-chip CAN/UART Bootstrap loader with boot
assist module (BAM)
Nexus® L2+ interface
Ambient temperature ranges: –40 to 125 °C or
–40 to 105 °C
Single 3.3 V or 5 V supply for I/Os and ADC
2 on-platform peripherals set with 2 INTC
16-channel eDMA controller with multiple
transfer request sources
June 2016
DocID18340 Rev 6
1/105
This is information on a product in full production.
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