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SPC5603BF2CLL6 PDF预览

SPC5603BF2CLL6

更新时间: 2024-09-18 14:59:23
品牌 Logo 应用领域
恩智浦 - NXP /
页数 文件大小 规格书
109页 2046K
描述
NXP 32-bit MCU, Power Arch core, 384KB Flash, 64MHz, -40/+85degC, Automotive Grade, QFP 100

SPC5603BF2CLL6 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Transferred包装说明:QFP, QFP100,.63SQ,20
Reach Compliance Code:unknown风险等级:5.65
位大小:32CPU系列:E200
JESD-30 代码:S-PQFP-G100JESD-609代码:e3
湿度敏感等级:3端子数量:100
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:PLASTIC封装代码:QFP
封装等效代码:QFP100,.63SQ,20封装形状:SQUARE
封装形式:FLATPACK电源:3.3/5 V
认证状态:Not QualifiedRAM(字节):28672
ROM(单词):393216ROM可编程性:FLASH
筛选级别:AEC-Q100速度:64 MHz
子类别:Microcontrollers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Matte Tin (Sn)端子形式:GULL WING
端子节距:0.5 mm端子位置:QUAD

SPC5603BF2CLL6 数据手册

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Freescale Semiconductor  
Data Sheet: Advance Information  
Document Number: MPC5604BC  
Rev. 11.1, 10/2013  
MPC5604B/C  
(20 x 20 x 1.4 mm)  
144 LQFP  
208 MAPBGA  
(17 x 17 x 1.7 mm)  
MPC5604B/C  
Microcontroller Data Sheet  
100 LQFP  
64 LQFP  
(14 x 14 x 1.4 mm)  
(10 x 10 x 1.4 mm)  
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4  
Package pinouts and signal descriptions. . . . . . . . . . . . . . . . . 8  
3.1 Package pinouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
3.2 Pad configuration during reset phases. . . . . . . . . . . . . 11  
3.3 Voltage supply pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.4 Pad types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12  
3.5 System pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
3.6 Functional ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13  
3.7 Nexus 2+ pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
3.8 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . 29  
3.9 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
3.10 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 30  
3.11 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30  
3.12 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 32  
3.13 Recommended operating conditions . . . . . . . . . . . . . . 33  
3.14 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35  
3.15 I/O pad electrical characteristics. . . . . . . . . . . . . . . . . . 36  
3.16 RESET electrical characteristics . . . . . . . . . . . . . . . . . 46  
3.17 Power management electrical characteristics . . . . . . . 48  
3.18 Power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . 54  
3.19 Flash memory electrical characteristics . . . . . . . . . . . . 56  
3.20 Electromagnetic compatibility (EMC) characteristics . . 58  
3.21 Fast external crystal oscillator (4 to 16 MHz) electrical  
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
3.22 Slow external crystal oscillator (32 kHz) electrical  
Features  
Single issue, 32-bit CPU core complex (e200z0)  
®
Compliant with the Power Architecture embedded category  
Includes an instruction set enhancement allowing variable  
length encoding (VLE) for code size footprint reduction. With  
the optional encoding of mixed 16-bit and 32-bit instructions, it  
is possible to achieve significant code size footprint reduction.  
2
3
Up to 512 KB on-chip code flash supported with the flash controller  
and ECC  
64 (4 × 16) KB on-chip data flash memory with ECC  
Up to 48 KB on-chip SRAM with ECC  
Memory protection unit (MPU) with 8 region descriptors and 32-byte  
region granularity  
Interrupt controller (INTC) with 148 interrupt vectors, including 16  
external interrupt sources and 18 external interrupt/wakeup sources  
Frequency modulated phase-locked loop (FMPLL)  
Crossbar switch architecture for concurrent access to peripherals, flash  
memory, or RAM from multiple bus masters  
Boot assist module (BAM) supports internal flash programming via a  
serial link (CAN or SCI)  
Timer supports input/output channels providing a range of 16-bit input  
capture, output compare, and pulse width modulation functions  
(eMIOS-lite)  
10-bit analog-to-digital converter (ADC)  
3 serial peripheral interface (DSPI) modules  
Up to 4 serial communication interface (LINFlex) modules  
Up to 6 enhanced full CAN (FlexCAN) modules with configurable  
buffers  
2
1 inter IC communication interface (I C) module  
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63  
3.23 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 65  
3.24 Fast internal RC oscillator (16 MHz) electrical  
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66  
3.25 Slow internal RC oscillator (128 kHz) electrical  
Up to 123 configurable general purpose pins supporting input and  
output operations (package dependent)  
Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz  
internal RC oscillator supporting autonomous wakeup with 1 ms  
resolution with max timeout of 2 seconds  
Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution  
1 System Module Timer (STM)  
Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class  
Two Plus standard  
Device/board boundary Scan testing supported with per Joint Test  
Action Group (JTAG) of IEEE (IEEE 1149.1)  
On-chip voltage regulator (VREG) for regulation of input supply for  
all internal levels  
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67  
3.26 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 69  
3.27 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 76  
Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86  
4.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . 86  
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97  
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . 97  
4
5
6
Appendix AAbbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106  
This document contains information on a product under development. Freescale reserves  
the right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2009-2013. All rights reserved.  

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