Datasheet > SP8402KGMPES

SP8402KGMPES

更新时间： 2024-11-11 22:36:19

品牌	Logo	应用领域
MITEL		逻辑集成电路光电二极管时钟
页数	文件大小	规格书
6页	111K
描述
Very Low Phase Noise Divider by 2N

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SP8402KGMPES 数据手册

SP8402

Very Low Phase Noise Divider by 2^N

DS3738 - 2.1 March 1994

The SP8402 is a very low phase noise divider which divides

bypowersoftwo. TheS0, S1, S2datainputsselectthedivision

ratiointherange2¹to2⁸. Specialcircuitstechniqueshavebeen

used to reduce the phase noise considerably below that

produced by standard dividers. The data inputs are CMOS or

TTL compatible.

N/C

+5V

N/C

The SP8402 is packaged in a 28 pin plastic SO package to

be compatible with the SP8400 and SP8401 devices.

GND

N/C

CLOCK INPUT

GND

N/C

FEATURES

OUTPUT

N/C

■ VerylowPhaseNoise(Typically-155to160dBc/Hzat1kHz

offset)

■ Supply Voltage 5V

+5V

N/C

+5V

N/C

ABSOLUTE MAXIMUM RATINGS

Supply Voltage

Output Current

6.5V

20mA

MP28

Storage Temperature Range

Maximum Clock Input Voltage

-55°C to +125°C

2.5V p-p

Fig.1 Pin connections - top view

ORDERING INFORMATION

SP8402 KG MPES (Commercial Grade)

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–130

–140

–150

–160

–170

100

Frequency (Hz)

10k

100k

Fig.2 Typical single sideband phase noise measured at 768MHz

12 3 4 5 6

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