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SP8402MP1T PDF预览

SP8402MP1T

更新时间: 2024-01-14 01:27:05
品牌 Logo 应用领域
加拿大卓联 - ZARLINK /
页数 文件大小 规格书
6页 464K
描述
Very Low Phase Noise Divider by 2N

SP8402MP1T 数据手册

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SP8402  
Very Low Phase Noise Divider by 2N  
September 2005  
The SP8402 is a very low phase noise divider which  
divides by powers of two. The S0, S1, S2 data inputs select  
the division ratio in the range 21 to 28. Special circuits  
techniques have been used to reduce the phase noise  
considerably below that produced by standard dividers. The  
data inputs are CMOS or TTL compatible.  
Ordering Information  
SP8402/KG/MPES 28 Pin SOIC Tubes  
SP8402/KG/MPFP 28 Pin SOIC* Tubes  
SP8402/KG/MP1T 28 Pin SOIC Tape & Reel  
The SP8402 is packaged in a 28 pin plastic SO package  
to be compatible with the SP8400 and SP8401 devices.  
*Pb Free Matte Tin  
FEATURES  
1
2
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
I Very low Phase Noise (Typically -155 to 160dBc/Hz at  
1kHz offset)  
I Supply Voltage 5V  
N/C  
N/C  
N/C  
+5V  
N/C  
N/C  
3
N/C  
4
V
N/C  
CC  
ABSOLUTE MAXIMUM RATINGS  
5
GND  
N/C  
Supply Voltage  
Output Current  
6.5V  
20mA  
6
CLOCK INPUT  
CLOCK INPUT  
CLOCK INPUT  
CLOCK INPUT  
GND  
N/C  
7
N/C  
Storage Temperature Range  
Maximum Clock Input Voltage  
-55°C to +125°C  
8
OUTPUT  
OUTPUT  
N/C  
2.5V p-p  
9
10  
11  
12  
13  
14  
V
V
+5V  
+5V  
N/C  
S0  
V
+5V  
CC  
CC  
CC  
N/C  
S2  
S1  
MP28  
Fig.1 Pin connections - top view  
0
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–130  
–140  
–150  
–160  
–170  
10  
100  
1k  
10k  
100k  
Frequency (Hz)  
Fig.2 Typical single sideband phase noise measured at 768MHz  
1
Zarlink Semiconductor Inc.  
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.  
Copyright 1994-2005, Zarlink Semiconductor Inc. All Rights Reserved.  

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