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SNJ54HCT645FKR PDF预览

SNJ54HCT645FKR

更新时间: 2024-11-02 19:57:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
15页 699K
描述
HCT SERIES, 8-BIT TRANSCEIVER, TRUE OUTPUT, CQCC20, CERAMIC, LCC-20

SNJ54HCT645FKR 技术参数

生命周期:Obsolete零件包装代码:QLCC
包装说明:QCCN,针数:20
Reach Compliance Code:unknown风险等级:5.84
其他特性:WITH DIRECTION CONTROL系列:HCT
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):150 pF逻辑集成电路类型:BUS TRANSCEIVER
位数:8功能数量:1
端口数量:2端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:CERAMIC, METAL-SEALED COFIRED封装代码:QCCN
封装形状:SQUARE封装形式:CHIP CARRIER
传播延迟(tpd):45 ns认证状态:Not Qualified
筛选级别:MIL-PRF-38535座面最大高度:2.03 mm
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD宽度:8.89 mm
Base Number Matches:1

SNJ54HCT645FKR 数据手册

 浏览型号SNJ54HCT645FKR的Datasheet PDF文件第2页浏览型号SNJ54HCT645FKR的Datasheet PDF文件第3页浏览型号SNJ54HCT645FKR的Datasheet PDF文件第4页浏览型号SNJ54HCT645FKR的Datasheet PDF文件第5页浏览型号SNJ54HCT645FKR的Datasheet PDF文件第6页浏览型号SNJ54HCT645FKR的Datasheet PDF文件第7页 
ꢊ ꢅꢆꢋꢌ ꢍꢎꢀ ꢆ ꢏꢋꢁꢀ ꢅꢐ ꢑ ꢒꢐ ꢏ  
SCLS019D − MARCH 1984 − REVISED AUGUST 2003  
D
D
Operating Voltage Range of 4.5 V to 5.5 V  
D
D
D
D
6-mA Output Drive at 5 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
True Logic  
D
Low Power Consumption, 80-µA Max I  
CC  
D
Typical t = 14 ns  
pd  
SN54HCT645 . . . J OR W PACKAGE  
SN74HCT645 . . . DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
SN54HCT645 . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
3
2
1
20 19  
18  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
A3  
A4  
A5  
A6  
A7  
B1  
B2  
B3  
B4  
4
5
6
7
8
17  
16  
15  
14 B5  
9 10 11 12 13  
GND  
description/ordering information  
These octal bus transceivers are designed for asynchronous two-way communication between data buses.  
These devices transmit data from the A bus to the B bus or from the B bus to the A bus, depending upon the  
level at the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the  
buses are effectively isolated.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HCT645N  
SN74HCT645N  
SN74HCT645DW  
SN74HCT645DWR  
SN74HCT645NSR  
SN74HCT645PW  
SN74HCT645PWR  
SN74HCT645PWT  
SNJ54HCT645J  
SOIC − DW  
SOP − NS  
HCT645  
HCT645  
−40°C to 85°C  
TSSOP − PW  
HT645  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HCT645J  
SNJ54HCT645W  
SNJ54HCT645FK  
SNJ54HCT645W  
SNJ54HCT645FK  
−55°C to 125°C  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢎ ꢁ ꢌꢐꢀꢀ ꢊ ꢆꢄ ꢐꢏꢓ ꢑꢀ ꢐ ꢁ ꢊꢆꢐꢗ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢖꢏ ꢊ ꢗ ꢎ ꢅꢆ ꢑꢊ ꢁ  
ꢦꢣ ꢥ ꢣ ꢠ ꢡ ꢘ ꢡ ꢥ ꢛ ꢩ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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