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SNJ54HCT646WR PDF预览

SNJ54HCT646WR

更新时间： 2024-11-02 21:12:03
品牌 Logo 应用领域
德州仪器 - TI 输出元件逻辑集成电路
页数 文件大小 规格书
13页 439K
描述
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, CDFP24, CERAMIC, DFP-24

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SNJ54HCT646WR 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP,针数：24
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.53其他特性：WITH DIRECTION CONTROL
系列：HCTJESD-30 代码：R-GDFP-F24
长度：14.355 mm负载电容（CL）：150 pF
逻辑集成电路类型：REGISTERED BUS TRANSCEIVER位数：8
功能数量：1端口数量：2
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：CERAMIC, GLASS-SEALED
封装代码：DFP封装形状：RECTANGULAR
封装形式：FLATPACK传播延迟（tpd）：80 ns
认证状态：Not Qualified筛选级别：MIL-PRF-38535
座面最大高度：2.29 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：9.09 mmBase Number Matches：1

SNJ54HCT646WR 数据手册

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SN54HCT646, SN74HCT646  
OCTAL BUS TRANSCEIVERS AND REGISTERS  
WITH 3-STATE OUTPUTS  
SCLS178C – MARCH 1984 – REVISED MARCH 2003  
Operating Voltage Range of 4.5 V to 5.5 V  
Low Power Consumption, 80-µA Max I  
Independent Registers for A and B Buses  
Multiplexed Real-Time and Stored Data  
True Data Paths  
CC  
Typical t = 12 ns  
pd  
±6-mA Output Drive at 5 V  
High-Current 3-State Outputs Can Drive Up  
To 15 LSTTL Loads  
Low Input Current of 1 µA Max  
Inputs Are TTL-Voltage Compatible  
SN54HCT646 . . . JT OR W PACKAGE  
SN74HCT646 . . . DW OR NT PACKAGE  
(TOP VIEW)  
SN54HCT646 . . . FK PACKAGE  
(TOP VIEW)  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
CLKAB  
SAB  
DIR  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
GND  
V
CC  
2
CLKBA  
SBA  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
3
4
3
2
1
28 27 26  
25  
A1  
A2  
A3  
NC  
A4  
OE  
B1  
B2  
NC  
B3  
B4  
B5  
5
6
7
8
9
4
24  
23  
22  
21  
20  
19  
5
6
7
8
A5 10  
11  
9
A6  
10  
11  
12  
12 13 14 15 16 17 18  
B8  
NC – No internal connection  
description/ordering information  
The ’HCT646 devices consist of bus-transceiver circuits with 3-state outputs, D-type flip-flops, and control  
circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers.  
Data on the A or B bus is clocked into the registers on the low-to-high transition of the appropriate clock (CLKAB  
or CLKBA) input. Figure 1 illustrates the four fundamental bus-management functions that can be performed  
with the ’HCT646 devices.  
Output-enable (OE) and direction-control (DIR) inputs control the transceiver functions. In the transceiver  
mode, data present at the high-impedance port can be stored in either or both registers.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP – NT  
SOIC – DW  
Tube  
SN74HCT646NT  
SN74HCT646DW  
SN74HCT646DWR  
SNJ54HCT646JT  
SNJ54HCT646W  
SNJ54HCT646FK  
SN74HCT646NT  
–40°C to 85°C  
–55°C to 125°C  
Tube  
HCT646  
Tape and reel  
Tube  
CDIP – JT  
CFP – W  
SNJ54HCT646JT  
SNJ54HCT646W  
SNJ54HCT646FK  
Tube  
LCCC – FK  
Tube  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...13

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