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SNJ54HC42FK PDF预览

SNJ54HC42FK

更新时间: 2024-11-02 04:10:43
品牌 Logo 应用领域
德州仪器 - TI 解码器
页数 文件大小 规格书
13页 413K
描述
4-LINE TO 10-LINE DECODERS (1 OF 10)

SNJ54HC42FK 技术参数

生命周期:Active零件包装代码:QLCC
包装说明:QCCN, LCC20,.35SQ针数:20
Reach Compliance Code:not_compliantECCN代码:EAR99
HTS代码:8542.39.00.01风险等级:5.56
系列:HC/UH输入调节:STANDARD
JESD-30 代码:S-CQCC-N20长度:8.89 mm
负载电容(CL):50 pF逻辑集成电路类型:DECIMAL DECODER/DRIVER
最大I(ol):0.0052 A位数:10
功能数量:1端子数量:20
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:INVERTED封装主体材料:CERAMIC, METAL-SEALED COFIRED
封装代码:QCCN封装等效代码:LCC20,.35SQ
封装形状:SQUARE封装形式:CHIP CARRIER
包装方法:TUBE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V最大电源电流(ICC):0.08 mA
Prop。Delay @ Nom-Sup:38 ns传播延迟(tpd):225 ns
认证状态:Not Qualified筛选级别:MIL-PRF-38535
座面最大高度:2.03 mm子类别:Decoder/Drivers
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子形式:NO LEAD端子节距:1.27 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:8.89 mmBase Number Matches:1

SNJ54HC42FK 数据手册

 浏览型号SNJ54HC42FK的Datasheet PDF文件第2页浏览型号SNJ54HC42FK的Datasheet PDF文件第3页浏览型号SNJ54HC42FK的Datasheet PDF文件第4页浏览型号SNJ54HC42FK的Datasheet PDF文件第5页浏览型号SNJ54HC42FK的Datasheet PDF文件第6页浏览型号SNJ54HC42FK的Datasheet PDF文件第7页 
ꢀꢁꢂ ꢃ ꢄꢅ ꢃ ꢆꢇ ꢀꢁ ꢈꢃ ꢄꢅ ꢃꢆ  
ꢃ ꢉꢊ ꢋꢁꢌ ꢍ ꢎ ꢏ ꢐ ꢉꢊ ꢋꢁꢌ ꢑꢌꢅ ꢎꢑ ꢌꢒ ꢀ ꢓ ꢏ ꢔꢕ ꢏꢐ ꢖ  
SCLS091D − DECEMBER 1982 − REVISED SEPTEMBER 2003  
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V  
Outputs Can Drive Up To 10 LSTTL Loads  
D
D
D
D
Low Input Current of 1 µA Max  
Full Decoding of Input Logic  
Low Power Consumption, 80-µA Max I  
All Outputs Are High for Invalid BCD  
Conditions  
CC  
Typical t = 14 ns  
pd  
4-mA Output Drive at 5 V  
Also for Applications as 3-Line to 8-Line  
Decoders  
SN54HC42 . . . J OR W PACKAGE  
SN74HC42 . . . D, N, OR NS PACKAGE  
(TOP VIEW)  
SN54HC42 . . . FK PACKAGE  
(TOP VIEW)  
0
V
A
B
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
CC  
3
2
1
20 19  
18  
1
B
2
3
4
5
6
7
8
2
C
17  
16  
15  
14  
3
C
D
9
NC  
D
NC  
4
4
5
9
5
9 10 11 12 13  
6
8
GND  
7
NC − No internal connection  
description/ordering information  
These decimal decoders consist of eight inverters and ten 4-input NAND gates. The inverters are connected  
in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid input logic  
ensures that all inputs remain off for all invalid input conditions.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP − N  
SOIC − D  
Tube of 25  
Tube of 40  
Reel of 2500  
Reel of 250  
Reel of 2000  
Tube of 25  
Tube of 150  
Tube of 55  
SN74HC42N  
SN74HC42N  
SN74HC42D  
SN74HC42DR  
SN74HC42DT  
SN74HC42NSR  
SNJ54HC42J  
SNJ54HC42W  
SNJ54HC42FK  
−40°C to 85°C  
HC42  
SOP − NS  
CDIP − J  
HC42  
SNJ54HC42J  
SNJ54HC42W  
SNJ54HC42FK  
−55°C to 125°C  
CFP − W  
LCCC − FK  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢎ ꢛ ꢤ ꢜ ꢔꢧ ꢢꢡ ꢟꢠ ꢡꢔ ꢝꢤ ꢦꢚ ꢞꢛ ꢟ ꢟꢔ ꢮꢋ ꢊꢉ ꢗꢒ ꢯ ꢉꢰꢱꢂ ꢰꢂꢇ ꢞꢦꢦ ꢤꢞ ꢜ ꢞ ꢝꢣ ꢟꢣꢜ ꢠ ꢞ ꢜ ꢣ ꢟꢣ ꢠꢟꢣ ꢧ  
ꢟ ꢣ ꢠ ꢟꢚ ꢛꢭ ꢔꢕ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
ꢢ ꢛꢦ ꢣꢠꢠ ꢔ ꢟꢩꢣ ꢜ ꢫꢚ ꢠꢣ ꢛ ꢔꢟꢣ ꢧꢨ ꢎ ꢛ ꢞꢦ ꢦ ꢔ ꢟꢩꢣ ꢜ ꢤꢜ ꢔ ꢧꢢꢡ ꢟꢠ ꢇ ꢤꢜ ꢔ ꢧꢢꢡ ꢟꢚꢔ ꢛ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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