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SNJ54HC540W PDF预览

SNJ54HC540W

更新时间： 2024-09-13 05:16:55
品牌 Logo 应用领域
德州仪器 - TI 驱动器输出元件
页数 文件大小 规格书
15页 508K
描述
OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS

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中文翻译

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SNJ54HC540W 技术参数

生命周期：Obsolete零件包装代码：DFP
包装说明：DFP, FL20,.3针数：20
Reach Compliance Code：unknown风险等级：5.84
其他特性：WITH DUAL OUTPUT ENABLE控制类型：ENABLE LOW
系列：HC/UHJESD-30 代码：R-GDFP-F20
长度：13.09 mm负载电容（CL）：150 pF
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.006 A
位数：8功能数量：1
端口数量：2端子数量：20
最高工作温度：125 °C最低工作温度：-55 °C
输出特性：3-STATE输出极性：INVERTED
封装主体材料：CERAMIC, GLASS-SEALED封装代码：DFP
封装等效代码：FL20,.3封装形状：RECTANGULAR
封装形式：FLATPACK包装方法：TUBE
电源：2/6 VProp。Delay @ Nom-Sup：30 ns
传播延迟（tpd）：224 ns认证状态：Not Qualified
筛选级别：MIL-PRF-38535座面最大高度：2.45 mm
子类别：Bus Driver/Transceivers最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：FLAT
端子节距：1.27 mm端子位置：DUAL
宽度：6.92 mmBase Number Matches：1

SNJ54HC540W 数据手册

 浏览型号SNJ54HC540W的Datasheet PDF文件第2页浏览型号SNJ54HC540W的Datasheet PDF文件第3页浏览型号SNJ54HC540W的Datasheet PDF文件第4页浏览型号SNJ54HC540W的Datasheet PDF文件第5页浏览型号SNJ54HC540W的Datasheet PDF文件第6页浏览型号SNJ54HC540W的Datasheet PDF文件第7页 
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SCLS007D − MARCH 1984 − REVISED AUGUST 2003  
SN54HC540 . . . J OR W PACKAGE  
SN74HC540 . . . DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
Wide Operating Voltage Range of 2 V to 6 V  
High-Current 3-State Outputs Drive Bus  
Lines Directly or Up To 15 LSTTL Loads  
D
D
D
D
D
Low Power Consumption, 80-µA Max I  
Typical t = 8 ns  
pd  
6-mA Output Drive at 5 V  
OE1  
A1  
A2  
A3  
A4  
A5  
A6  
A7  
A8  
V
CC  
OE2  
Y1  
1
2
3
4
5
6
7
8
9
20  
19  
18  
CC  
17 Y2  
16 Y3  
15 Y4  
14 Y5  
13 Y6  
12 Y7  
11 Y8  
Low Input Current of 1 µA Max  
Data Flow-Through Pinout (All Inputs on  
Opposite Side From Outputs)  
description/ordering information  
GND 10  
These octal buffers and line drivers feature the  
performance of the popular ’HC240 series and  
offer a pinout with inputs and outputs on opposite  
sides of the package. This arrangement greatly  
facilitates printed circuit board layout.  
SN54HC540 . . . FK PACKAGE  
(TOP VIEW)  
The 3-state control gate is a 2-input NOR. If either  
output-enable (OE1 or OE2) input is high, all eight  
outputs are in the high-impedance state. The  
’HC540 devices provide inverted data at the  
outputs.  
3
2
1
20 19  
18  
Y1  
Y2  
Y3  
A3  
A4  
A5  
A6  
A7  
4
5
6
7
8
17  
16  
15 Y4  
14  
Y5  
9 10 11 12 13  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
†
PACKAGE  
T
A
PDIP − N  
Tube of 20  
Tube of 25  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
Reel of 2000  
Reel of 250  
Tube of 20  
Tube of 85  
Tube of 55  
SN74HC540N  
SN74HC540N  
SN74HC540DW  
SN74HC540DWR  
SN74HC540NSR  
SN74HC540DBR  
SN74HC540PW  
SN74HC540PWR  
SN74HC540PWT  
SNJ54HC540J  
SOIC − DW  
HC540  
SOP − NS  
HC540  
HC540  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
HC540  
CDIP − J  
CFP − W  
LCCC − FK  
SNJ54HC540J  
SNJ54HC540W  
SNJ54HC540FK  
SNJ54HC540W  
SNJ54HC540FK  
−55°C to 125°C  
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

中文翻译

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