ꢀꢁ ꢂꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢈ
ꢊ ꢅꢋꢌꢍ ꢎꢏꢋ ꢐꢑ ꢒ ꢓ ꢍꢔ ꢑꢏꢓ ꢍꢊ ꢑ ꢀ
ꢕ ꢔꢋ ꢄ ꢅ ꢍꢒ ꢌꢖ
SCLS136D − DECEMBER 1982 − REVISED AUGUST 2003
D
D
D
D
D
D
D
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
D
D
D
Direct Clear Input
Individual Data Input to Each Flip-Flop
Low Power Consumption, 80-µA Max I
Applications Include:
− Buffer/Storage Registers
− Shift Registers
CC
Typical t = 12 ns
pd
4-mA Output Drive at 5 V
− Pattern Generators
Low Input Current of 1 µA Max
Contain Eight Flip-Flops With Single-Rail
Outputs
description
SN54HC273 . . . FK PACKAGE
(TOP VIEW)
SN54HC273 . . . J OR W PACKAGE
SN74HC273 . . . DB, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
3
2
1
20 19
18
8D
17 7D
2D
2Q
3Q
3D
4D
4
5
6
7
8
16
15
14
7Q
6Q
6D
9 10 11 12 13
GND
description/ordering information
These circuits are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 20
Tube of 25
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
Reel of 2000
Reel of 250
Tube of 20
Tube of 85
Tube of 55
SN74HC273N
SN74HC273N
SN74HC273DW
SN74HC273DWR
SN74HC273NSR
SN74HC273DBR
SN74HC273PW
SN74HC273PWR
SN74HC273PWT
SNJ54HC273J
SOIC − DW
HC273
SOP − NS
HC273
HC273
−40°C to 85°C
SSOP − DB
TSSOP − PW
HC273
CDIP − J
CFP − W
LCCC − FK
SNJ54HC273J
SNJ54HC273W
SNJ54HC273FK
−55°C to 125°C
SNJ54HC273W
SNJ54HC273FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
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