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SNJ54ABT373FK PDF预览

SNJ54ABT373FK

更新时间： 2024-11-25 01:12:59
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德州仪器 - TI 输出元件
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21页 909K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SNJ54ABT373FK 数据手册

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SN54ABT373, SN74ABT373  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCBS155D – JANUARY 1991 – REVISED MAY 1997  
SN54ABT373 . . . J OR W PACKAGE  
SN74ABT373 . . . DB, DW, N, OR PW PACKAGE  
(TOP VIEW)  
State-of-the-Art EPIC-ΙΙB BiCMOS Design  
Significantly Reduces Power Dissipation  
Latch-Up Performance Exceeds 500 mA Per  
JEDEC Standard JESD-17  
OE  
1Q  
V
CC  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
Typical V  
(Output Ground Bounce) < 1 V  
8Q  
8D  
7D  
OLP  
at V  
= 5 V, T = 25°C  
1D  
2D  
CC  
A
High-Drive Outputs (–32-mA I , 64-mA I  
OH  
)
OL  
2Q  
3Q  
16 7Q  
15 6Q  
Package Options Include Plastic  
Small-Outline (DW), Shrink Small-Outline  
(DB), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Chip Carriers (FK),  
Ceramic Flat (W) Package, and Plastic (N)  
and Ceramic (J) DIPs  
14  
13  
12  
11  
3D  
4D  
4Q  
GND  
6D  
5D  
5Q  
LE  
description  
SN54ABT373 . . . FK PACKAGE  
(TOP VIEW)  
The eight latches of the ’ABT373 are transparent  
D-type latches. While the latch-enable (LE) input  
is high, the Q outputs follow the data (D) inputs.  
When LE is taken low, the Q outputs are latched  
at the logic levels set up at the D inputs.  
3
2
1
20 19  
18  
2D  
2Q  
3Q  
3D  
4D  
8D  
7D  
7Q  
6Q  
4
5
6
7
8
17  
16  
15  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low logic levels) or  
a
14 6D  
9 10 11 12 13  
high-impedance state. In the high-impedance  
state, the outputs neither load nor drive the bus  
lines significantly. The high-impedance state and  
increased drive provide the capability to drive bus  
lines without need for interface or pullup  
components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54ABT373 is characterized for operation over the full military temperature range of –55°C to 125°C. The  
SN74ABT373 is characterized for operation from –40°C to 85°C.  
FUNCTION TABLE  
(each latch)  
INPUTS  
OUTPUT  
Q
OE  
L
LE  
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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SNJ54ABT373FK 替代型号

型号 品牌 替代类型 描述 数据表
5962-9074601M2A TI

完全替代

 具有三态输出的八路透明 D 型锁存器 | FK | 20 | -55 to 125
SNJ54BCT373FK TI

完全替代

 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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