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SN75ALS197N-00 PDF预览

SN75ALS197N-00

更新时间： 2024-11-20 14:44:55
品牌 Logo 应用领域
德州仪器 - TI 光电二极管接口集成电路
页数 文件大小 规格书
21页 787K
描述
LINE RECEIVER, PDIP16

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SN75ALS197N-00 技术参数

生命周期：Obsolete包装说明：DIP,
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.67
输入特性：DIFFERENTIAL SCHMITT TRIGGER接口集成电路类型：LINE RECEIVER
接口标准：V.10; V.11; X.26; X.27JESD-30 代码：R-PDIP-T16
长度：19.305 mm功能数量：1
端子数量：16最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE认证状态：Not Qualified
最大接收延迟：22 ns接收器位数：4
座面最大高度：5.08 mm最大供电电压：5.25 V
最小供电电压：4.75 V标称供电电压：5 V
表面贴装：NO技术：BIPOLAR
温度等级：COMMERCIAL端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
宽度：7.62 mmBase Number Matches：1

SN75ALS197N-00 数据手册

 浏览型号SN75ALS197N-00的Datasheet PDF文件第2页浏览型号SN75ALS197N-00的Datasheet PDF文件第3页浏览型号SN75ALS197N-00的Datasheet PDF文件第4页浏览型号SN75ALS197N-00的Datasheet PDF文件第5页浏览型号SN75ALS197N-00的Datasheet PDF文件第6页浏览型号SN75ALS197N-00的Datasheet PDF文件第7页 
SN75ALS197  
QUADRUPLE DIFFERENTIAL LINE RECEIVER  
SLLS045B – JANUARY 1989 – REVISED MAY 1995  
D OR N PACKAGE  
(TOP VIEW)  
Meets or Exceeds the Requirements of ITU  
Recommendations V.10, V.11, X.26, and  
X.27  
V
1B  
1A  
1
2
3
4
5
6
7
8
16  
15  
14  
CC  
Designed for Multipoint Bus Transmission  
on Long Bus Lines in Noisy Environments  
4B  
4A  
1Y  
Designed to Operate Up to 20 Mbaud  
3-State Outputs  
13 4Y  
G
12  
11  
10  
9
G
2Y  
3Y  
3A  
3B  
2A  
Common-Mode Input Voltage Range  
– 7 V to 7 V  
2B  
GND  
Input Sensitivity . . . ±300 mV  
Input Hysteresis . . . 120 mV Typ  
High-Input Impedance . . . 12 kΩ Min  
Operates from Single 5-V Supply  
Low Supply-Current Requirement  
35 mA Max  
Improved Speed and Power Consumption  
Compared to AM26LS32A  
description  
The SN75ALSI97 is a monolithic, quadruple line receiver with 3-state outputs designed using advanced,  
low-power, Schottky technology. This technology provides combined improvements in bar design, tooling  
production, and wafer fabrication. This, in turn, provides significantly lower power requirements and permits  
much higher data throughput than other designs. The device meets the specifications of ITU Recommendations  
V.10, V.11, X.26, and X.27. It features 3-state outputs that permit direct connection to a bus-organized system  
with a fail-safe design that ensures the outputs will always be high if the inputs are open.  
The device is optimized for balanced, multipoint bus transmission at rates up to 20 megabits per second. The  
input features high-input impedance, input hysteresis for increased noise immunity, and an input sensitivity of  
±300 mV over a common-mode input voltage range of –7 V to 7 V. It also features active-high and active-low  
enablefunctionsthatarecommontothefourchannels. TheSN75ALS197isdesignedforoptimumperformance  
when used with the SN75ALS192 quadruple differential line driver.  
The SN75ALS197 is characterized for operation from 0°C to 70°C.  
FUNCTION TABLE  
(each receiver)  
ENABLES  
DIFFERENTIAL INPUTS  
A–B  
OUTPUT  
Y
G
G
H
X
X
L
H
H
V
ID  
≥ 0.3 V  
H
X
X
L
?
?
– 0.3 V < V < 0.3 V  
ID  
H
X
X
L
L
L
V
ID  
≤ – 0.3 V  
X
L
H
Z
H
X
X
L
H
H
Open  
H = high level, L = low level, X = irrelevant, ? = indeterminate,  
Z = high impedance (off)  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...21

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