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SN75C1154NS PDF预览

SN75C1154NS

更新时间: 2024-11-24 12:59:31
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德州仪器 - TI 驱动器
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SN75C1154NS 数据手册

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SN75C1154  
QUADRUPLE LOW-POWER DRIVERS/RECEIVERS  
SLLS151C – DECEMBER 1988 – REVISED MARCH 1997  
DW OR N PACKAGE  
(TOP VIEW)  
Meets or Exceeds the Requirements of  
ANSI EIA/TIA-232-E and ITU  
Recommendation V.28  
V
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
V
CC  
DD  
Very Low Power Consumption  
5 mW Typ  
1RA  
1DY  
2RA  
2DY  
3RA  
3DY  
4RA  
4DY  
1RY  
1DA  
2RY  
2DA  
3RY  
3DA  
4RY  
4DA  
GND  
Wide Driver Supply Voltage . . . ±4.5 V  
to ±15 V  
Driver Output Slew Rate Limited to  
30 V/µs Max  
Receiver Input Hysteresis . . . 1000 mV Typ  
Push-Pull Receiver Outputs  
V
SS  
On-Chip Receiver 1-µs Noise Filter  
Functionally interchangeable With Motorola  
MC145404  
description  
The SN75C1154 is a low-power BiMOS device containing four independent drivers and receivers that are used  
tointerfacedataterminalequipment(DTE)withdatacircuit-terminatingequipment(DCE). Thisdevicehasbeen  
designed to conform to ANSI EIA/TIA-232-E. The drivers and receivers of the SN75C1154 are similar to those  
of the SN75C188 quadruple driver and SN75C189A quadruple receiver, respectively. The drivers have a  
controlled output slew rate that is limited to a maximum of 30 V/µs and the receivers have filters that reject input  
noise pulses of shorter than 1 µs. Both these features eliminate the need for external components.  
The SN75C1154 is designed using low-power techniques in a BiMOS technology. In most applications, the  
receivers contained in these devices interface to single inputs of peripheral devices such as ACEs, UARTs, or  
microprocessors. By using sampling, such peripheral devices are usually insensitive to the transition times of  
the input signals. If this is not the case or for other uses, it is recommended that the SN75C1154 receiver outputs  
be buffered by single Schmitt input gates or single gates of the HCMOS, ALS, or 74F logic families.  
The SN75C1154 is characterized for operation from 0°C to 70°C.  
logic symbol  
logic diagram (positive logic)  
2
4
6
8
3
5
7
9
19  
17  
15  
13  
18  
16  
14  
12  
typical of each receiver  
1RA  
2RA  
3RA  
4RA  
1DY  
2DY  
3DY  
4DY  
1RY  
2RY  
3RY  
4RY  
1DA  
2DA  
3DA  
4DA  
2, 4, 6, 8  
RA  
19, 17, 15, 13  
18, 16, 14, 12  
RY  
DA  
typical of each driver  
3, 5, 7, 9  
DY  
This symbol is in accordance with ANSI/IEEE Std 91-1984 and  
IEC Publication 617-12.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 1997, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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