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SN74LVTH125IPWREP PDF预览

SN74LVTH125IPWREP

更新时间： 2024-12-01 02:58:43
品牌 Logo 应用领域
德州仪器 - TI 驱动光电二极管输出元件逻辑集成电路
页数 文件大小 规格书
9页 431K
描述
3.3-V ABT QUADRUPLE BUS BUFFER WITH 3-STATE OUTPUTS

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中文翻译

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SN74LVTH125IPWREP 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：TSSOP
包装说明：TSSOP, TSSOP14,.25针数：14
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：0.69
控制类型：ENABLE LOW计数方向：UNIDIRECTIONAL
系列：LVTJESD-30 代码：R-PDSO-G14
JESD-609代码：e4长度：5 mm
负载电容（CL）：50 pF逻辑集成电路类型：BUS DRIVER
最大I（ol）：0.064 A湿度敏感等级：1
位数：1功能数量：4
端口数量：2端子数量：14
最高工作温度：85 °C最低工作温度：-40 °C
输出特性：3-STATE输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法：TR
峰值回流温度（摄氏度）：260电源：3.3 V
最大电源电流（ICC）：7 mAProp。Delay @ Nom-Sup：3.9 ns
传播延迟（tpd）：4.9 ns认证状态：Not Qualified
座面最大高度：1.2 mm子类别：Bus Driver/Transceivers
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED翻译：N/A
宽度：4.4 mmBase Number Matches：1

SN74LVTH125IPWREP 数据手册

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SCBS765 − NOVEMBER 2003  
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
D
D
D
Enhanced Product-Change Notification  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
†
Qualification Pedigree  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
3.3-V V  
)
CC  
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
PW PACKAGE  
(TOP VIEW)  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
= 3.3 V, T = 25°C  
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
CC  
A
†
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
4A  
4Y  
3OE  
3A  
3Y  
8
GND  
description/ordering information  
This bus buffer is designed specifically for low-voltage (3.3-V) V  
a TTL interface to a 5-V system environment.  
operation, but with the capability to provide  
CC  
The SN74LVTH125 features independent line drivers with 3-state outputs. Each output is in the high-impedance  
state when the associated output-enable (OE) input is high.  
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors  
with the bus-hold circuitry is not recommended.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
‡
T
A
PACKAGE  
−40°C to 85°C  
TSSOP − PW Tape and reel  
SN74LVTH125IPWREP  
LH125EP  
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
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Copyright 2003, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...9

中文翻译

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SN74LVTH125IPWREP 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVTH125PWR TI

完全替代

 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVTH125PW TI

完全替代

 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVTH125PWG4 TI

完全替代

 3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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