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SN74LVTH125PW PDF预览

SN74LVTH125PW

更新时间: 2024-11-28 23:06:23
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理PC
页数 文件大小 规格书
15页 411K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

SN74LVTH125PW 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Active零件包装代码:TSSOP
包装说明:TSSOP-14针数:14
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.56Samacsys Confidence:
Samacsys Status:ReleasedSamacsys PartID:305894
Samacsys Pin Count:14Samacsys Part Category:Integrated Circuit
Samacsys Package Category:OtherSamacsys Footprint Name:SOP65P640X120-14N
Samacsys Released Date:2017-01-12 12:59:53Is Samacsys:N
控制类型:ENABLE LOW计数方向:UNIDIRECTIONAL
系列:LVTJESD-30 代码:R-PDSO-G14
JESD-609代码:e4长度:5 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.064 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:TUBE
峰值回流温度(摄氏度):260电源:3.3 V
最大电源电流(ICC):7 mAProp。Delay @ Nom-Sup:3.9 ns
传播延迟(tpd):4.9 ns认证状态:Not Qualified
座面最大高度:1.2 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:BICMOS温度等级:INDUSTRIAL
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:0.65 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:4.4 mm
Base Number Matches:1

SN74LVTH125PW 数据手册

 浏览型号SN74LVTH125PW的Datasheet PDF文件第2页浏览型号SN74LVTH125PW的Datasheet PDF文件第3页浏览型号SN74LVTH125PW的Datasheet PDF文件第4页浏览型号SN74LVTH125PW的Datasheet PDF文件第5页浏览型号SN74LVTH125PW的Datasheet PDF文件第6页浏览型号SN74LVTH125PW的Datasheet PDF文件第7页 
ꢌ ꢍꢌ ꢎꢅ ꢏꢐꢆ ꢑ ꢒꢏꢓꢔ ꢒꢕꢄ ꢖ ꢐꢒꢀ ꢐ ꢒꢗ ꢗꢖ ꢔ  
SCBS703I − AUGUST 1997 − REVISED OCTOBER 2003  
D
D
D
D
Support Mixed-Mode Signal Operation (5-V  
Input and Output Voltages With 3.3-V V  
D
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
)
CC  
Support Unregulated Battery Operation  
Down to 2.7 V  
D
D
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
SN74LVTH125 . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVTH125 . . . FK PACKAGE  
(TOP VIEW)  
SN54LVTH125 . . . J OR W PACKAGE  
SN74LVTH125 . . . D, DB, DGV, NS,  
OR PW PACKAGE  
(TOP VIEW)  
1
14  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
3
2
1
20 19  
18 4A  
1A  
1Y  
13 4OE  
12 4A  
1Y  
NC  
2
3
4
5
6
4
5
6
7
8
17  
16  
15  
14  
NC  
4Y  
4A  
4Y  
3OE  
3A  
3Y  
11  
10  
9
2OE  
2A  
4Y  
2OE  
NC  
3OE  
3A  
NC  
3OE  
2Y  
2A  
9 10 11 12 13  
7
8
8
GND  
NC − No internal connection  
description/ordering information  
These bus buffers are designed specifically for low-voltage (3.3-V) V  
provide a TTL interface to a 5-V system environment.  
operation, but with the capability to  
CC  
The ’LVTH125 devices feature independent line drivers with 3-state outputs. Each output is in the  
high-impedance state when the associated output-enable (OE) input is high.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
QFN − RGY  
SOIC − D  
Tape and reel  
Tube  
SN74LVTH125RGYR  
SN74LVTH125D  
LXH125  
LVTH125  
Tape and reel  
Tape and reel  
Tape and reel  
Tube  
SN74LVTH125DR  
SN74LVTH125NSR  
SN74LVTH125DBR  
SN74LVTH125PW  
SN74LVTH125PWR  
SN74LVTH125DGVR  
SNJ54LVTH125J  
SOP − NS  
LVTH125  
LXH125  
−40°C to 85°C  
SSOP − DB  
TSSOP − PW  
LXH125  
Tape and reel  
Tape and reel  
Tube  
TVSOP − DGV  
CDIP − J  
LXH125  
SNJ54LVTH125J  
SNJ54LVTH125W  
SNJ54LVTH125FK  
CFP − W  
Tube  
SNJ54LVTH125W  
SNJ54LVTH125FK  
−55°C to 125°C  
LCCC − FK  
Tube  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
ꢒ ꢁ ꢄꢖꢀꢀ ꢚ ꢆꢇ ꢖꢔꢘ ꢙꢀ ꢖ ꢁ ꢚꢆꢖꢓ ꢛꢜ ꢝꢞ ꢟꢠꢡ ꢢꢣꢤ ꢥꢛ ꢡꢠ ꢥꢛꢦ ꢝꢥꢞ ꢕꢔ ꢚ ꢓ ꢒ ꢧꢆ ꢙꢚ ꢁ  
ꢪꢦ ꢩ ꢦ ꢣ ꢤ ꢛ ꢤ ꢩ ꢞ ꢍ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

SN74LVTH125PW 替代型号

型号 品牌 替代类型 描述 数据表
SN74LVT125PWR TI

完全替代

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SN74LVT125PW TI

完全替代

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SN74LVTH125DBR TI

完全替代

3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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