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SN74LVCZ245ANSRE4 PDF预览

SN74LVCZ245ANSRE4

更新时间: 2024-01-15 08:24:40
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德州仪器 - TI 总线收发器输出元件
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15页 535K
描述
OCTAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS

SN74LVCZ245ANSRE4 数据手册

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SN74LVCZ245A  
OCTAL BUS TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCES275G – JUNE 1999 – REVISED AUGUST 2003  
DB, DW, N, NS, OR PW PACKAGE  
(TOP VIEW)  
Operates From 2.7 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max t of 6.3 ns at 3.3 V  
pd  
1
2
3
4
5
6
7
8
9
10  
20  
19  
18  
17  
16  
15  
14  
13  
12  
11  
DIR  
A1  
V
CC  
OE  
B1  
B2  
B3  
B4  
B5  
B6  
B7  
B8  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
A2  
= 3.3 V, T = 25°C  
A
A3  
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
A4  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
A5  
I
and Power-Up 3-State Support Hot  
off  
A6  
Insertion  
A7  
Supports Mixed-Mode Signal Operation on  
All Ports (5-V Input/Output Voltage With  
A8  
GND  
3.3-V V  
)
CC  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
description/ordering information  
This octal bus transceiver is designed for 2.7-V to 3.6-V V  
operation.  
CC  
The SN74LVCZ245A is designed for asynchronous communication between data buses. The device transmits  
data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the  
direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so the buses are  
effectively isolated.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator  
in a mixed 3.3-V/5-V system environment.  
When V  
is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down.  
CC  
However, to ensure the high-impedance state above 1.5 V, OE should be tied to V  
the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup resistor;  
CC  
This device is fully specified for hot-insertion applications using I and power-up 3-state. The I circuitry  
off  
off  
disables the outputs, preventing damaging current backflow through the device when it is powered down. The  
power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down,  
which prevents driver conflict.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
PDIP – N  
Tube of 20  
SN74LVCZ245AN  
SN74LVCZ245AN  
Tube of 25  
SN74LVCZ245ADW  
SN74LVCZ245ADWR  
SN74LVCZ245ANSR  
SN74LVCZ245ADBR  
SN74LVCZ245APW  
SN74LVCZ245APWR  
SOIC – DW  
LVCZ245A  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 70  
SOP – NS  
LVCZ245A  
CV245A  
CV245A  
CV245A  
–40°C to 85°C  
SSOP – DB  
TSSOP – PW  
Reel of 2000  
Reel of 250  
SN74LVCZ245APWT  
CV245A  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines  
are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2003, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  

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