SN74LVT125

更新时间： 2024-02-07 05:56:42

品牌	Logo	应用领域
德州仪器 - TI		输出元件
页数	文件大小	规格书
7页	119K
描述
3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS

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SN74LVT125 数据手册

SN54LVT125, SN74LVT125

3.3-V ABT QUADRUPLE BUS BUFFERS

WITH 3-STATE OUTPUTS

SCBS133D – MAY 1992 – REVISED JULY 1995

SN54LVT125 . . . J PACKAGE

SN74LVT125 . . . D, DB, OR PW PACKAGE

(TOP VIEW)

State-of-the-Art Advanced BiCMOS

Technology (ABT) Design for 3.3-V

Operation and Low-Static Power

Dissipation

1OE

2OE

4OE

Support Mixed-Mode Signal Operation (5-V

Input and Output Voltages With 3.3-V V

)

3OE

Support Unregulated Battery Operation

Down to 2.7 V

Typical V

< 0.8 V at V

(Output Ground Bounce)

OLP

= 3.3 V, T = 25°C

GND

ESD Protection Exceeds 2000 V Per

MIL-STD-883C, Method 3015; Exceeds

200 V Using Machine Model

(C = 200 pF, R = 0)

SN54LVT125 . . . FK PACKAGE

(TOP VIEW)

Latch-Up Performance Exceeds 500 mA

Per JEDEC Standard JESD-17

20 19

18 4A

Bus-Hold Data Inputs Eliminate the Need

for External Pullup Resistors

Support Live Insertion

2OE

3OE

Package Options Include Plastic

Small-Outline (D), Shrink Small-Outline

(DB), and Thin Shrink Small-Outline (PW)

9 10 11 12 13

Packages, Ceramic Chip Carriers (FK), and

Ceramic (J) DIPs

NC – No internal connection

description

These bus buffers are designed specifically for low-voltage (3.3-V) V

provide a TTL interface to a 5-V system environment.

operation, but with the capability to

The ′LVT125 feature independent line drivers with 3-state outputs. Each output is in the high-impedance state

when the associated output-enable (OE) input is high.

Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74LVT125 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count

and functionality of standard small-outline packages in less than half the printed-circuit-board area.

The SN54LVT125 is characterized for operation over the full military temperature range of –55°C to 125°C. The

SN74LVT125 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains PRODUCTION

DATA information current as of publication date. Products conform to

specifications per the terms of Texas Instruments standard warranty.

Production processing does not necessarily include testing of all

parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

12 3 4 5 6 7

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与SN74LVT125相关器件

型号	品牌	获取价格	描述	数据表
SN74LVT125_06	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125D	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DB	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBLE	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBR	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DBRG4	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DG4	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DR	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DRG4	TI	获取价格	3.3-V ABT QUADRUPLE BUS BUFFERS WITH 3-STATE OUTPUTS
SN74LVT125DW	TI	获取价格	LVT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, PLASTIC, SOP-14

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