SN74LVC1G32
SINGLE 2-INPUT POSITIVE-OR GATE
www.ti.com
SCES219O–APRIL 1999–REVISED FEBRUARY 2007
FEATURES
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
•
•
•
•
•
Supports 5-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Inputs Accept Voltages to 5.5 V
Max tpd of 3.6 ns at 3.3 V
ESD Protection Exceeds JESD 22
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–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
Low Power Consumption, 10-µA Max ICC
± 24-mA Output Drive at 3.3 V
1000-V Charged-Device Model (C101)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
5
4
A
B
VCC
Y
1
2
3
5
A
B
VCC
1
2
3
A
B
5
4
VCC
GND
4
GND
Y
GND
Y
YZP PACKAGE
(BOTTOM VIEW)
DRY PACKAGE
(TOP VIEW)
3
2
1
4
GND
B
Y
1
2
3
6
5
4
A
B
VCC
NC
Y
5
A
VCC
GND
NC – No internal connection
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single 2-input positive-OR gate is designed for 1.65-V to 5.5-V VCC operation.
Y = A + B or Y = A • B
The SN74LVC1G32 performs the Boolean function
in positive logic.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 1999–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.