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SN74LVC1G00DBV

更新时间： 2024-11-26 22:28:07
品牌 Logo 应用领域
德州仪器 - TI 输入元件
页数 文件大小 规格书
17页 442K
描述
SINGLE 2-INPUT POSITIVE-NAND GATE

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中文翻译

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SN74LVC1G00DBV 数据手册

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SCES212T − APRIL 1999 − REVISED JUNE 2005  
D
Available in the Texas Instruments  
NanoStarand NanoFreePackages  
D
D
D
I
Supports Partial-Power-Down Mode  
off  
Operation  
D
D
D
D
D
Supports 5-V V  
Operation  
Latch-Up Performance Exceeds 100 mA Per  
JESD 78, Class II  
CC  
Inputs Accept Voltages to 5.5 V  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Max t of 3.8 ns at 3.3 V  
pd  
Low Power Consumption, 10-µA Max I  
CC  
24-mA Output Drive at 3.3 V  
− 1000-V Charged-Device Model (C101)  
YEA, YEP, YZA,  
DBV PACKAGE  
(TOP VIEW)  
DCK PACKAGE  
(TOP VIEW)  
DRL PACKAGE  
(TOP VIEW)  
OR YZP PACKAGE  
(BOTTOM VIEW)  
3
2
1
4
5
Y
GND  
B
1
2
3
5
A
B
V
CC  
A
B
V
1
2
3
5
CC  
1
2
3
5
A
B
V
Y
CC  
V
A
CC  
4
GND  
Y
4
GND  
Y
4
GND  
See mechanical drawings for dimensions.  
description/ordering information  
This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V  
operation.  
CC  
The SN74LVC1G00 performs the Boolean function Y = A • B or Y = A + B in positive logic.  
NanoStarand NanoFreepackage technology is a major breakthrough in IC packaging concepts, using the  
die as the package.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
NanoStar and NanoFree are trademarks of Texas Instruments.  
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Copyright 2005, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...17

中文翻译

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