Datasheet > SN74LVC1G00_10

SN74LVC1G00_10

更新时间： 2024-11-27 11:52:15

品牌	Logo	应用领域
德州仪器 - TI		输入元件
页数	文件大小	规格书
16页	660K
描述
SINGLE 2-INPUT POSITIVE-NAND GATE

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SN74LVC1G00_10 数据手册

SN74LVC1G00

www.ti.com

SCES212V –APRIL 1999–REVISED FEBRUARY 2010

SINGLE 2-INPUT POSITIVE-NAND GATE

Check for Samples: SN74LVC1G00

FEATURES

•

Available in the Texas Instruments NanoStar™

Package

•

I_offSupports Partial-Power-Down Mode

Operation

•

Supports 5-V V_CCOperation

Inputs Accept Voltages to 5.5 V

Max t_pdof 3.8 ns at 3.3 V

Low Power Consumption, 10-mA Max I_CC

±24-mA Output Drive at 3.3 V

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

–

2000-V Human-Body Model (A114-A)

1000-V Charged-Device Model (C101)

YZP PACKAGE

(BOTTOM VIEW)

DBV PACKAGE

(TOP VIEW)

DCK PACKAGE

(TOP VIEW)

DRL PACKAGE

(TOP VIEW)

GND

V_CC

GND

See mechanical drawings for dimensions.

DESCRIPTION/ORDERING INFORMATION

This single 2-input positive-NAND gate is designed for 1.65-V to 5.5-V V_CCoperation.

The SN74LVC1G00 performs the Boolean function Y = A ● B or Y = A + B in positive logic.

NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

This device is fully specified for partial-power-down applications using I_off. The I_offcircuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

ORDERING INFORMATION⁽¹⁾

T_A

PACKAGE⁽²⁾

ORDERABLE PART NUMBER

TOP-SIDE MARKING⁽³⁾

_ _ _ CA_

NanoStar™ – WCSP (DSBGA)

0.23-mm Large Bump – YZP

(Pb-free)

SN74LVC1G00YZPR

Reel of 3000 SN74LVC1G00DBVR

Reel of 250 SN74LVC1G00DBVT

Reel of 3000 SN74LVC1G00DCKR

Reel of 250 SN74LVC1G00DCKT

Reel of 4000 SN74LVC1G00DRLR

SOT (SOT-23) – DBV

C00_

CA_

–40°C to 85°C

SOT (SC-70) – DCK

SOT (SOT-553) – DRL

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

(3) DBV/DCK/DRL: The actual top-side marking has one additional character that designates the wafer fab/assembly site.

YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following

character to designate the wafer fab/assembly site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, ● = Pb-free).

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

12 3 4 5 6 7...16

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与SN74LVC1G00_10相关器件

型号	品牌	获取价格	描述	数据表
SN74LVC1G00_101	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBV	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVR	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVR	UMW	获取价格	逻辑集成电路
SN74LVC1G00DBVRE4	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVRG4	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVT	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVTE4	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DBVTG4	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE
SN74LVC1G00DCK	TI	获取价格	SINGLE 2-INPUT POSITIVE-NAND GATE

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