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SN74LVC16543DGG

更新时间： 2024-11-03 23:09:43
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16-BIT REGISTERED TRANSCEIVER WITH 3-STATE OUTPUTS

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SN74LVC16543  
16-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCAS317A – NOVEMBER 1993 – REVISED OCTOBER 1995  
DGG OR DL PACKAGE  
(TOP VIEW)  
Member of the Texas Instruments  
Widebus Family  
EPIC (Enhanced-Performance Implanted  
CMOS) Submicron Process  
1OEAB  
1LEAB  
1CEAB  
GND  
1OEBA  
1LEBA  
1CEBA  
GND  
1B1  
1B2  
1
2
3
4
5
6
7
8
9
56  
55  
54  
53  
52  
51  
50  
49  
48  
Typical V  
< 0.8 V at V  
(Output Ground Bounce)  
OLP  
= 3.3 V, T = 25°C  
CC  
A
Typical V  
> 2 V at V  
(Output V  
Undershoot)  
OHV  
CC  
OH  
1A1  
1A2  
= 3.3 V, T = 25°C  
A
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
V
V
CC  
CC  
1A3  
1A4  
1B3  
1B4  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
1A5 10  
GND 11  
47 1B5  
46 GND  
1A6  
1B6  
12  
45  
Package Options Include Plastic 300-mil  
Shrink Small-Outline (DL) and Thin Shrink  
Small-Outline (DGG) Packages  
1A7 13  
1A8 14  
2A1 15  
2A2 16  
2A3 17  
GND 18  
2A4 19  
2A5 20  
2A6 21  
44 1B7  
43 1B8  
42 2B1  
41 2B2  
40 2B3  
39 GND  
38 2B4  
37 2B5  
36 2B6  
description  
This 16-bit registered transceiver is designed for  
low-voltage (3.3-V) V operation.  
CC  
The SN74LVC16543 can be used as two 8-bit  
transceivers or one 16-bit transceiver. Separate  
latch-enable (LEAB or LEBA) and output-enable  
(OEAB or OEBA) inputs are provided for each  
register to permit independent control in either  
direction of data flow.  
V
22  
35  
V
CC  
CC  
2A7 23  
34 2B7  
2A8 24  
33 2B8  
GND 25  
32 GND  
31 2CEBA  
30 2LEBA  
29 2OEBA  
2CEAB 26  
2LEAB 27  
2OEAB 28  
The A-to-B enable (CEAB) input must be low in  
order to enter data from A or to output data from  
B. If CEAB is low and LEAB is low, the A-to-B  
latches are transparent; a subsequent low-to-high  
transition of LEAB puts the A latches in the  
storage mode. With CEAB and OEAB both low,  
the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to  
A is similar but requires using the CEBA, LEBA, and OEBA inputs.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.  
The SN74LVC16543 is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC and Widebus are trademarks of Texas Instruments Incorporated.  
Copyright 1995, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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