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SN74LV373ADGV

更新时间： 2024-11-17 22:37:07
品牌 Logo 应用领域
德州仪器 - TI 锁存器输出元件
页数 文件大小 规格书
8页 155K
描述
OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

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SN54LV373A, SN74LV373A  
OCTAL TRANSPARENT D-TYPE LATCHES  
WITH 3-STATE OUTPUTS  
SCLS407A – APRIL 1998 – REVISED JUNE 1998  
SN54LV373A . . . J OR W PACKAGE  
SN74LV373A . . . DB, DGV, DW, NS, OR PW PACKAGE  
(TOP VIEW)  
EPIC (Enhanced-Performance Implanted  
CMOS) Process  
Typical V  
< 0.8 V at V , T = 25°C  
(Output Ground Bounce)  
OLP  
OE  
1Q  
1D  
2D  
2Q  
3Q  
3D  
4D  
4Q  
V
CC  
8Q  
8D  
CC  
A
1
2
3
4
5
6
7
8
9
20  
19  
18  
Typical V  
> 2 V at V , T = 25°C  
(Output V  
Undershoot)  
OHV  
CC  
OH  
A
17 7D  
16 7Q  
15 6Q  
14 6D  
13 5D  
12 5Q  
11 LE  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
Package Options Include Plastic  
Small-Outline (DW, NS), Shrink  
GND 10  
Small-Outline (DB), Thin Very Small-Outline  
(DGV), and Thin Shrink Small-Outline (PW)  
Packages, Ceramic Flat (W) Packages, Chip  
Carriers (FK), and DIPs (J)  
SN54LV373A . . . FK PACKAGE  
(TOP VIEW)  
description  
3
2
1
20 19  
18  
8D  
7D  
7Q  
2D  
2Q  
3Q  
3D  
4D  
4
5
6
7
8
The ’LV373A devices are octal transparent D-type  
latches designed for 2-V to 5.5-V V operation.  
17  
16  
CC  
15 6Q  
14  
9 10 11 12 13  
While the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is  
taken low, the Q outputs are latched at the logic  
levels set up at the D inputs.  
6D  
A buffered output-enable (OE) input can be used  
to place the eight outputs in either a normal logic  
state (high or low) or the high-impedance state. In  
the high-impedance state, the outputs neither  
load nor drive the bus lines significantly. The  
high-impedance state and increased drive  
provide the capability to drive bus lines without  
need for interface or pullup components.  
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered  
while the outputs are in the high-impedance state.  
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup  
CC  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
The SN54LV373A is characterized for operation over the full military temperature range of –55°C to 125°C.  
The SN74LV373A is characterized for operation from –40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1998, Texas Instruments Incorporated  
UNLESS OTHERWISE NOTED this document contains PRODUCTION  
DATA information current as of publication date. Products conform to  
specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all  
parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
12345678

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