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ꢋꢌꢍ ꢎꢏꢐ ꢐ ꢌꢑꢀ ꢉꢁꢒ ꢄ ꢓꢁꢌ ꢒ ꢑꢓ ꢅ ꢌꢑ ꢀ
ꢔ ꢓꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗ ꢏꢕ ꢘꢏ ꢕꢀ
SCLS398G − APRIL 1998 − REVISED APRIL 2005
SN54LV367A . . . J OR W PACKAGE
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 7 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
= 3.3 V, T = 25°C
A
2OE
2A2
2Y2
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
12 2A1
11
10
9
2Y1
1A4
1Y4
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
SN54LV367A . . . FK PACKAGE
(TOP VIEW)
− 1000-V Charged-Device Model (C101)
description/ordering information
3
2
1
20 19
18
2A2
2Y2
NC
1Y1
1A2
NC
The ’LV367A devices are hex buffers and line
4
5
6
7
8
drivers designed for 2-V to 5.5-V V
operation.
17
16
CC
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
15 2A1
14
9 10 11 12 13
1Y2
1A3
2Y1
The ’LV367A devices are organized as dual 4-line
and 2-line buffers/drivers with active-low
output-enable (1OE and 2OE) inputs. When OE is
low, the device passes noninverted data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
NC − No internal connection
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 40
SN74LV367AD
SOIC − D
LV367A
Reel of 2500
Reel of 2000
Reel of 2000
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
SN74LV367ADR
SN74LV367ANSR
SN74LV367ADBR
SN74LV367APWR
SN74LV367APWT
SN74LV367ADGVR
SNJ54LV367AJ
SOP − NS
74LV367A
LV36A
SSOP − DB
−40°C to 85°C
TSSOP − PW
LV367A
TVSOP − DGV
CDIP − J
LV367A
SNJ54LV367AJ
SNJ54LV367AW
SNJ54LV367AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV367AW
SNJ54LV367AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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