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SN74LV164PW PDF预览

SN74LV164PW

更新时间： 2024-11-06 12:59:43
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器
页数 文件大小 规格书
8页 162K
描述
LV/LV-A/LVX/H SERIES, 8-BIT RIGHT SERIAL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO14

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SN74LV164PW 技术参数

生命周期：Obsolete包装说明：TSSOP, TSSOP14,.25
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.22计数方向：RIGHT
系列：LV/LV-A/LVX/HJESD-30 代码：R-PDSO-G14
长度：5 mm逻辑集成电路类型：SERIAL IN PARALLEL OUT
位数：8功能数量：1
端子数量：14最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装等效代码：TSSOP14,.25封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.2 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
触发器类型：POSITIVE EDGE宽度：4.4 mm
Base Number Matches：1

SN74LV164PW 数据手册

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SCLS191B − FEBRUARY 1993 − REVISED APRIL 1996  
SN54LV164 . . . J OR W PACKAGE  
SN74LV164 . . . D, DB, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
EPIC (Enhanced-Performance Implanted  
CMOS) 2-µ Process  
Typical V  
(Output Ground Bounce)  
OLP  
< 0.8 V at V , T = 25°C  
CC  
A
A
B
V
CC  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
Q
Q
Q
Q
H
G
F
> 2 V at V , T = 25°C  
CC  
A
Q
A
B
ESD Protection Exceeds 2000 V Per  
MIL-STD-883C, Method 3015; Exceeds  
200 V Using Machine Model  
(C = 200 pF, R = 0)  
Q
Q
C
D
E
Q
CLR  
CLK  
GND  
8
D
D
Latch-Up Performance Exceeds 250 mA  
Per JEDEC Standard JESD-17  
SN54LV164 . . . FK PACKAGE  
(TOP VIEW)  
Package Options Include Plastic  
Small-Outline (D), Shrink Small-Outline  
(DB), Thin Shrink Small-Outline (PW),  
Ceramic Flat (W) Packages, Chip Carriers  
(FK), and (J) 300-mil DIPs  
3
2
1
20 19  
18  
Q
Q
4
5
6
7
8
G
A
NC  
NC  
17  
16  
description  
Q
F
Q
B
15 NC  
14  
9 10 11 12 13  
NC  
These 8-bit parallel-out serial shift registers are  
designed for 2.7-V to 5.5-V V operation.  
Q
Q
C
E
CC  
The ’LV164 feature AND-gated serial (A and B)  
inputs and an asynchronous clear (CLR) input.  
The gated serial inputs permit complete control  
over incoming data as a low at either input inhibits  
entry of the new data and resets the first flip-flop  
to the low level at the next clock pulse. A high-level  
NC − No internal connection  
input enables the other input, which then determines the state of the first flip-flop. Data at the serial inputs can  
be changed while the clock is high or low, provided the minimum setup time requirements are met. Clocking  
occurs on the low-to-high-level transition of the clock (CLK) input.  
The SN74LV164 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count  
and functionality of standard small-outline packages in less than half the printed-circuit-board area.  
The SN54LV164 is characterized for operation over the full military temperature range of −55°C to 125°C. The  
SN74LV164 is characterized for operation from −40°C to 85°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
EPIC is a trademark of Texas Instruments Incorporated.  
Copyright 1996, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443  
12345678

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