SN74LS73

更新时间： 2024-02-18 17:45:23

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		触发器
页数	文件大小	规格书
3页	78K
描述
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

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技术参数
数据手册

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SN74LS73 技术参数

生命周期：	Contact Manufacturer	包装说明：	,
Reach Compliance Code：	unknown	HTS代码：	8542.39.00.01
风险等级：	5.58	逻辑集成电路类型：	J-K FLIP-FLOP
Base Number Matches：	1

SN74LS73 数据手册

SN54/74LS73A

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

The SN54LS/74LS73A offers individual J, K, clear, and clock inputs. These

dual flip-flops are designed so that when the clock goes HIGH, the inputs are

enabled and data will be accepted. The logic level of the J and K inputs may

be allowed to change when the clock pulse is HIGH and the bistable will per-

form according to the truth table as long as minimum set-up times are ob-

served. Input data is transferred to the outputs on the negative-going edge of

the clock pulse.

DUAL JK NEGATIVE

EDGE-TRIGGERED FLIP-FLOP

LOW POWER SCHOTTKY

LOGIC DIAGRAM (Each Flip-Flop)

J SUFFIX

CERAMIC

CASE 632-08

13 (8)

12 (9)

N SUFFIX

PLASTIC

CASE 646-06

CLEAR

2 (6)

3 (10)

14 (7)

1 (15)

CLOCK (CP)

D SUFFIX

SOIC

CASE 751A-02

ORDERING INFORMATION

SN54LSXXJ

SN74LSXXN

SN74LSXXD

Ceramic

Plastic

SOIC

MODE SELECT — TRUTH TABLE

INPUTS

OUTPUTS

OPERATING MODE

LOGIC SYMBOL

Reset (Clear)

Toggle

Load “0” (Reset)

Load “1” (Set)

Hold

H, h = HIGH Voltage Level

L, I = LOW Voltage Level

X = Don’t Care

l, h (q) = Lower case letters indicate the state of the referenced input (or output) one set-up time

l, h (q) = prior to the HIGH to LOW clock transition.

= PIN 4

GND = PIN 11

FAST AND LS TTL DATA

5-68

12 3

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与SN74LS73相关器件

型号	品牌	描述	获取价格	数据表
SN74LS73A	TI	DUAL J-K FLIP-FLOPS WITH CLEAR	获取价格
SN74LS73AD	TI	DUAL J-K FLIP-FLOPS WITH CLEAR	获取价格
SN74LS73AD3	TI	IC,FLIP-FLOP,DUAL,J/K TYPE,LS-TTL,SOP,14PIN,PLASTIC	获取价格
SN74LS73ADR	TI	暂无描述	获取价格
SN74LS73ADRE4	TI	LS SERIES, DUAL NEGATIVE EDGE TRIGGERED J-K FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14, GREEN	获取价格
SN74LS73AJ	ROCHESTER	J-K Flip-Flop	获取价格